component
MS5314
Public Made by Adomby adom
Hangzhou Ruimeng Tech Digital To Analog Converters (DAC), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 16d ago |
| viewers | 16d ago |
| ms5314-etched.glb | 16d ago |
| ms5314-etched.step | 16d ago |
| ms5314-hero.glb | 16d ago |
| ms5314-hero.overlay.json | 16d ago |
| ms5314.glb | 16d ago |
| ms5314.kicad_mod | 16d ago |
| ms5314.kicad_sym | 16d ago |
| ms5314.lbr | 16d ago |
| ms5314.step | 16d ago |
| package.json | 16d ago |
| page.json | 16d ago |
| README.md | 16d ago |
MS5314
Hangzhou Ruimeng Tech · Digital To Analog Converters (DAC) · MSOP-10
MS5314 from Hangzhou Ruimeng Tech, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply pin, with the device specified for 2.5 V to 5.5 V operation (4.5-5.5 V for 5 V supply, 2.7-3.3 V for 3 V supply in the recommended conditions). |
| 2 | OUTA | output | Analog voltage output of DAC channel A, which swings from 0 to VDD-0.4 V at RL = 10 kΩ. |
| 3 | OUTB | output | Analog voltage output of DAC channel B, which swings from 0 to VDD-0.4 V at RL = 10 kΩ. |
| 4 | OUTC | output | Analog voltage output of DAC channel C, which swings from 0 to VDD-0.4 V at RL = 10 kΩ. |
| 5 | REFIN | input | Reference voltage input, with an allowed range of 0 to VDD-1.5 V; inputs above VDD/2 cause output saturation at large DAC codes. |
| 6 | OUTD | output | Analog voltage output of DAC channel D, which swings from 0 to VDD-0.4 V at RL = 10 kΩ. |
| 7 | GND | power_in | Ground reference pin; the datasheet recommends connecting it to the system analog ground plane and decoupling VDD to GND with a 0.1 µF ceramic capacitor placed close to the device. |
| 8 | DIN | input | Serial data input carrying the 16-bit word (channel address A1/A0, PD, LDAC, and 10-bit DAC data), with setup time of at least 5 ns and hold time of at least 4.5 ns relative to SCLK. |
| 9 | SCLK | input | Serial clock input, with a maximum rate of 20 MHz in the recommended operating conditions, minimum period of 33 to 40 ns depending on VDD. |
| 10 | SYNC | input | Frame synchronization input; the serial frame begins when SYNC goes low, with SYNC-to-SCLK falling-edge setup of at least 13 to 16 ns and minimum high time of 33 to 80 ns depending on VDD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Hangzhou Ruimeng Tech |
| Package | MSOP-10 |
| Category | Data Acquisition |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute max) | VDD | -0.3 | 7 | V | 4 | ||
| Digital input voltage range (absolute max) | VIN | -0.3 | V | 4 | |||
| Reference input voltage range (absolute max) | VREFIN | -0.3 | V | 4 | |||
| Operating temperature range | TA | -40 | 105 | ℃ | 4 | ||
| Storage temperature range | Tstg | -60 | 150 | ℃ | 4 | ||
| Maximum junction temperature | Jt | 150 | ℃ | 4 | |||
| Soldering temperature | 260 | ℃ | 4 | ||||
| Supply voltage, 5V supply | 4.5 | 5 | 5.5 | V | 5V 供电 | 4 | |
| Supply voltage, 3V supply | 2.7 | 3 | 3.3 | V | 3V 供电 | 4 | |
| Digital input high voltage VIH | VIH | 2 | V | VDD＝2.7V | 4 | ||
| Digital input high voltage VIH | VIH | 2.4 | V | VDD＝5.5V | 4 | ||
| Digital input low voltage VIL | VIL | 0.6 | V | VDD＝2.7V | 4 | ||
| Digital input low voltage VIL | VIL | 1 | V | VDD＝5.5V | 4 | ||
| Load resistance | 2 | 10 | KΩ | 4 | |||
| Load capacitance | 100 | pF | 4 | ||||
| SCLK rate | 20 | MHz | 4 | ||||
| Differential nonlinearity (DNL) | DNL | -1 | 0.5 | 1 | LSB | 见注 2 | 5 |
| Integral nonlinearity (INL) | INL | -1 | 0.5 | 1 | LSB | 见注 3 | 5 |
| Zero-scale offset error | -3 | 3 | mV | 见注 4 | 5 | ||
| Gain error | -3 | 0.15 | 3 | %of FS | 见注 6 | 5 | |
| Output voltage | 0 | V | RL＝10KΩ | 5 | |||
| Output load regulation accuracy | 0.1 | 0.25 | %of FS | RL＝2KΩ到 10KΩ | 5 | ||
| Reference input voltage range | 0 | V | 见注 10 | 6 | |||
| Digital input high-level current | -1 | 1 | uA | VI＝VDD | 6 | ||
| Digital input low-level current | -1 | 1 | uA | VI＝0V | 6 | ||
| Supply current, 5V supply | 1.6 | 2.4 | mA | 5V 供电，无负载，加 CLOCK，输入接 0V 或 VDD | 6 | ||
| Supply current, 3V supply | 1.2 | 1.6 | mA | 3V 供电，无负载，加 CLOCK，输入接 0V 或 VDD | 6 | ||
| Settling time to ±0.5LSB | Ts | 3 | 5.5 | V/us | CL＝100pF，RL＝10KΩ | 6 | |
| SCLK period | t1 | 40 | ns | VDD=2.5V-3.6V | 7 | ||
| SCLK period | t1 | 33 | ns | VDD=3.6V-5.5V | 7 | ||
| SCLK high time | t2 | 16 | ns | VDD=2.5V-3.6V | 7 | ||
| SCLK high time | t2 | 13 | ns | VDD=3.6V-5.5V | 7 | ||
| SCLK low time | t3 | 16 | ns | VDD=2.5V-3.6V | 7 | ||
| SCLK low time | t3 | 13 | ns | VDD=3.6V-5.5V | 7 | ||
| SYNC to SCLK falling edge setup time | t4 | 16 | ns | VDD=2.5V-3.6V | 7 | ||
| SYNC to SCLK falling edge setup time | t4 | 13 | ns | VDD=3.6V-5.5V | 7 | ||
| Data setup time | t5 | 5 | ns | VDD=2.5V-3.6V | 7 | ||
| Data hold time | t6 | 4.5 | ns | VDD=2.5V-3.6V | 7 | ||
| SCLK falling edge to SYNC rising edge time | t7 | 0 | ns | VDD=2.5V-3.6V | 7 | ||
| Minimum SYNC high time | t8 | 80 | ns | VDD=2.5V-3.6V | 7 | ||
| Minimum SYNC high time | t8 | 33 | ns | VDD=3.6V-5.5V | 7 | ||
| Zero-scale offset temperature coefficient | -12 | ppm/℃ | 见注 5 | 5 | |||
| Gain error temperature coefficient | 12 | ppm/℃ | 见注 7 | 5 | |||
| Zero-scale PSRR | PSRR | -80 | dB | 见注 8 和注 9 | 5 | ||
| Full-scale PSRR | PSRR | -80 | dB | 见注 9 | 5 | ||
| Reference input resistance | 10 | MΩ | 6 | ||||
| Reference feedthrough | -75 | dB | REFIN=1Vpp(1KHz)+1.024 V（注 11） | 6 | |||
| Reference input bandwidth | 1 | MHz | REFIN = 0.2Vpp+1.024V（大信号） | 6 | |||
| Digital input capacitance | 3 | pF | 6 | ||||
| Power-down current | 10 | nA | 6 | ||||
| Slew rate | SR | 5 | V/us | CL＝100pF，RL＝10KΩ，Vo＝10%到90%，Vref＝2.048，1.024 | 6 | ||
| Settling time to ±0.5LSB (code change, complete) | Ts(c) | 1 | us | 到±0.5LSB，CL＝100pF，RL＝10KΩ | 6 | ||
| Glitch energy | 10 | nV-sec | 从 1FF 到 200 | 6 | |||
| Signal-to-noise ratio (SNR) | SNR | 74 | dB | fs＝400KSPS，fout＝1.1KHz 正弦波，CL＝100pF，RL＝10KΩ，BW＝20KHz | 6 | ||
| Signal-to-noise and distortion (S/(N+D)) | S/(N+D) | 66 | dB | fs＝400KSPS，fout＝1.1KHz 正弦波，CL＝100pF，RL＝10KΩ，BW＝20KHz | 6 | ||
| Total harmonic distortion (THD) | THD | -68 | dB | fs＝400KSPS，fout＝1.1KHz 正弦波，CL＝100pF，RL＝10KΩ，BW＝20KHz | 6 | ||
| Spurious-free dynamic range (SFDR) | SFDR | 70 | dB | fs＝400KSPS，fout＝1.1KHz 正弦波，CL＝100pF，RL＝10KΩ，BW＝20KHz | 6 |
CAD (KiCad official)
- Symbol:
MS5314 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
ms5314-etched.step/ms5314-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ms5314.step/ms5314.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Hangzhou Ruimeng Tech datasheet (11 pp, sha256
79c7a3ced86dafbc, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).