component
MS520
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Hangzhou Ruimeng Tech RFID ICs, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownMS520
Hangzhou Ruimeng Tech · RFID ICs · VQFN-32-EP(5x5)
MS520 from Hangzhou Ruimeng Tech, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | N.C. | unconnected | Not connected (datasheet pin type I, marked not connected). |
| 2 | PVDD | power_in | Pin supply; VDD(PVDD) is specified at 1.6 V to 3.6 V (1.8 V typical) and must be equal to or lower than VDDD. |
| 3 | DVDD | power_in | Digital supply; VDDD is specified at 2.5 V to 3.6 V (3.3 V typical) and must equal VDDA and VDD(TVDD). |
| 4 | DVSS | power_in | Digital ground; the exposed die pad under the package is optional and may be connected to this pin. |
| 5 | PVSS | power_in | Pin supply ground. |
| 6 | NRSTPD | input | Reset and power-down input: low level enables hard power-down (cuts internal current, stops the oscillator and disconnects input pins), and a rising edge enables reset. |
| 7 | TIN | input | Test signal input, also used as the active-antenna receive input when TIN/TOUT interface is used; must be tied to SVDD or PVSS when unused. |
| 8 | TOUT | output | Test signal output, used for test and for driving an active antenna circuit via the TOUT interface. |
| 9 | SVDD | power_in | Supply for the TIN and TOUT pins; specified at 1.6 V to 3.6 V and must be connected to DVDD, PVDD or another supply pin when unused. |
| 10 | TVSS | power_in | Ground of the TX1 transmitter output stage. |
| 11 | TX1 | output | Transmitter 1 output delivering the 13.56 MHz energy carrier modulated by the transmit envelope; drives the antenna through passive matching and filtering. |
| 12 | TVDD | power_in | Transmitter supply powering the TX1 and TX2 output stages; specified at 2.5 V to 3.6 V. |
| 13 | TX2 | output | Transmitter 2 output delivering the 13.56 MHz energy carrier modulated by the transmit envelope. |
| 14 | TVSS | power_in | Ground of the TX2 transmitter output stage. |
| 15 | AVDD | power_in | Analog supply; VDDA is specified at 2.5 V to 3.6 V (3.3 V typical) and must equal VDDD and VDD(TVDD). |
| 16 | VMID | passive | Internal reference voltage node (datasheet type P); no electrical limit is stated for it in the text. |
| 17 | RX | input | RF signal input; the pin voltage is clamped by internal diodes to AVSS and AVDD, with input voltage range -1 V to VDDA +1 V. |
| 18 | AVSS | power_in | Analog ground. |
| 19 | AUX1 | output | Auxiliary output for test signals; DAC outputs are current sources, so a 510 Ω pull-down resistor is recommended. |
| 20 | AUX2 | output | Auxiliary output for test signals; DAC outputs are current sources, so a 510 Ω pull-down resistor is recommended. |
| 21 | OSCIN | input | Inverting input of the crystal oscillator amplifier, also the input for an external clock (27.12 MHz, 40-60 % duty cycle). |
| 22 | OSCOUT | output | Inverting output of the crystal oscillator amplifier for a 27.12 MHz crystal. |
| 23 | IRQ | output | Interrupt request output indicating an interrupt event; can be configured as push-pull or open-drain. |
| 24 | NSS | input | SPI slave select input. |
| 25 | D1 | bidirectional | Test port D1 (I/O), usable only as an output when the test pin output driver is enabled; limited to D1-D4 when SPI is used. |
| 26 | D2 | bidirectional | Test port D2 (I/O). |
| 27 | D3 | bidirectional | Test port D3 (I/O). |
| 28 | D4 | bidirectional | Test port D4 (I/O). |
| 29 | SCK | bidirectional | Multiplexed pin: test port D5 (I/O) and SPI serial clock input SCK, which must be generated by the host. |
| 30 | MOSI | bidirectional | Multiplexed pin: test port D6 (I/O) and SPI master-out/slave-in MOSI (I/O). |
| 31 | MISO | bidirectional | Multiplexed pin: test port D7 (I/O) and SPI master-in/slave-out MISO (I/O). |
| 32 | N.C. | unconnected | Not connected (datasheet pin type I, marked not connected). |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Hangzhou Ruimeng Tech |
| Package | VQFN-32-EP(5x5) |
| Category | RF And Wireless |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog supply voltage (absolute maximum) | VDDA | -0.5 | 4 | V | 47 | ||
| Digital supply voltage (absolute maximum) | VDDD | -0.5 | 4 | V | 47 | ||
| PVDD supply voltage (absolute maximum) | VDD(PVDD) | -0.5 | 4 | V | 47 | ||
| TVDD supply voltage (absolute maximum) | VDD(TVDD) | -0.5 | 4 | V | 47 | ||
| SVDD supply voltage (absolute maximum) | VDD(SVDD) | -0.5 | 4 | V | 47 | ||
| Junction temperature | Tj | 100 | ℃ | 47 | |||
| ESD voltage HBM | VESD | 2000 | V | HBM；150Ω；100pF；JESD22-A144-B | 47 | ||
| ESD voltage MM | VESD | 200 | V | MM；0.75μH；200pF；JESD22-A144-A | 47 | ||
| Analog supply voltage (recommended) | VDDA | 2.5 | 3.3 | 3.6 | V | VDD(PVDD)≤VDDA=VDDD=VDD(TVDD); VSSA =VSSD =VSS(PVSS) =VSS(TVSS) =0V | 48 |
| Digital supply voltage (recommended) | VDDD | 2.5 | 3.3 | 3.6 | V | VDD(PVDD)≤VDDA=VDDD=VDD(TVDD); VSSA =VSSD =VSS(PVSS) =VSS(TVSS) =0V | 48 |
| TVDD supply voltage (recommended) | VDD(TVDD) | 2.5 | 3.3 | 3.6 | V | VDD(PVDD)≤VDDA=VDDD=VDD(TVDD); VSSA =VSSD =VSS(PVSS) =VSS(TVSS) =0V | 48 |
| PVDD supply voltage (recommended) | VDD(PVDD) | 1.6 | 1.8 | 3.6 | V | VDD(PVDD)≤VDDA=VDDD=VDD(TVDD); VSSA =VSSD =VSS(PVSS) =VSS(TVSS) =0V | 48 |
| SVDD supply voltage (recommended) | VDD(SVDD) | 1.6 | 3.6 | V | VSSA =VSSD =VSS(PVSS) =VSS(TVSS) =0V | 48 | |
| Ambient temperature (QFN32) | Tamb | -25 | 85 | ℃ | QFN32 | 48 | |
| NRSTPD input leakage current | ILI | -1 | 1 | μA | 49 | ||
| TIN input leakage current | ILI | -1 | 1 | μA | 49 | ||
| RX input voltage | Vi | -1 | V | 49 | |||
| OSCIN input leakage current | ILI | -1 | 1 | μA | 49 | ||
| D1-D7 input leakage current | ILI | -1 | 1 | μA | 49 | ||
| D1-D7 output current high | IOH | 4 | mA | VDD(PVDD)= 3V | 49 | ||
| D1-D7 output current low | IOL | 4 | mA | VDD(PVDD)= 3V | 49 | ||
| TOUT output current high | IOH | 4 | mA | VDD(PVDD)= 3V | 50 | ||
| TOUT output current low | IOL | 4 | mA | VDD(PVDD)= 3V | 50 | ||
| IRQ output current high | IOH | 4 | mA | VDD(PVDD)= 3V | 50 | ||
| IRQ output current low | IOL | 4 | mA | VDD(PVDD)= 3V | 50 | ||
| AUX1 and AUX2 output current high | IOH | 4 | mA | VDD(PVDD)= 3V | 50 | ||
| AUX1 and AUX2 output current low | IOL | 4 | mA | VDD(PVDD)= 3V | 50 | ||
| TX1 and TX2 output voltage low | VOL | 0.15 | V | VDD(TVDD)=3V; IDD(TVDD)=32mA; CWGsP[5:0]=0Fh | 50 | ||
| TX1 and TX2 output voltage low | VOL | 0.4 | V | VDD(TVDD)=3V; IDD(TVDD)=80mA; CWGsP[5:0]=0Fh | 50 | ||
| TX1 and TX2 output voltage low | VOL | 0.24 | V | VDD(TVDD)=2.5V; IDD(TVDD)=32mA; CWGsP[5:0]=0Fh | 50 | ||
| TX1 and TX2 output voltage low | VOL | 0.64 | V | VDD(TVDD)=2.5V; IDD(TVDD)=80mA; CWGsP[5:0]=0Fh | 50 | ||
| Power-down current, hard power-down | Ipd | 5 | μA | VDDA=VDDD=VDD(TVDD)=VDD(PVDD)=3V; hard power-down NRSTPD=LOW | 50 | ||
| Power-down current, soft power-down | Ipd | 10 | μA | VDDA=VDDD=VDD(TVDD)=VDD(PVDD)=3V; soft power-down, RF level detector off | 51 | ||
| PVDD supply current | IDD(PVDD) | 40 | mA | Pin PVDD | 51 | ||
| TVDD supply current | IDD(TVDD) | 60 | 100 | mA | Pin TVDD; continuous wave | 51 | |
| SVDD supply current | IDD(SVDD) | 4 | mA | Pin SVDD | 51 | ||
| Clock duty cycle | δclk | 40 | 50 | 60 | % | 51 | |
| Clock jitter time | tjit | 10 | ps | RMS | 51 | ||
| Crystal equivalent series resistance | ESR | 100 | Ω | 51 | |||
| Crystal power dissipation | Pxtal | 50 | 100 | mW | 51 | ||
| SPI low-level pulse width SCK | tWL | 50 | ns | SCK | 52 | ||
| SPI high-level pulse width SCK | tWH | 50 | ns | SCK | 52 | ||
| SPI data input hold time after SCK high | th(SCKH-D) | 25 | ns | SCK to changing MOSI | 52 | ||
| SPI data input setup time to SCK high | tsu(D-SCKH) | 25 | ns | changing MOSI to SCK | 52 | ||
| SPI data output hold time after SCK low | th(SCKL-Q) | 25 | ns | SCK to changing MISO | 52 | ||
| SCK low to NSS high time | t(SCKL-NSSH) | 0 | ns | 52 | |||
| NSS high time before communication | tNHNL | 50 | ns | 52 |
CAD (KiCad official)
- Symbol:
MS520 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
ms520-etched.step/ms520-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ms520.step/ms520.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Hangzhou Ruimeng Tech datasheet (62 pp, sha256
7870c75ac44eea56, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).