# MS51PC0AE

**Nuvoton Tech** · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

MS51PC0AE from Nuvoton Tech, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | nRESET / P2.0 | input | Schmitt-trigger input for hardware device reset, where a low on this pin resets the device; it has an internal pull-up for power-on reset with an external capacitor to VSS, and doubles as Port 2 bit 0 input when CONFIG0.2 (RPD) is programmed as 0. |
| 2 | P3.0 | bidirectional | Port 3 bit 0 with alternate functions ADC_CH1, SPI0_MOSI, UART2_TXD, SC0_CLK, INT0 and OSCIN, where OSCIN is the external clock input when EXTEN[1:0] = 11b. |
| 3 | P1.7 | bidirectional | Port 1 bit 7 with alternate functions ADC_CH0, SPI0_CLK, UART2_RXD, SC0_DAT and external interrupt INT1. |
| 4 | VSS | power_in | Ground potential. |
| 5 | P1.6 | bidirectional | Port 1 bit 6 with alternate functions I2C0_SDA, UART1_TXD and ICE_DAT (ICE data input or output). |
| 6 | VDD | power_in | Supply voltage VDD for operation. |
| 7 | P1.5 | bidirectional | Port 1 bit 5 with alternate functions PWM0_CH5, PWM3_CH1, IC7, SPI0_SS and UART3_TXD. |
| 8 | P2.5 | bidirectional | Port 2 bit 5 with alternate functions ADC_CH15, SPI0_MISO, UART3_RXD and SC1_DAT. |
| 9 | P3.6 | bidirectional | Port 3 bit 6 with alternate function UART1_TXD (UART1 transmit data output). |
| 10 | P3.7 | bidirectional | Port 3 bit 7 with alternate function UART1_RXD (UART1 receive input). |
| 11 | P1.4 | bidirectional | Port 1 bit 4 with alternate functions ADC_CH14, PWM0_CH1, PWM1_CH1, I2C0_SDA and PWM0_Brake (PWM0 fault brake input). |
| 12 | P1.3 | bidirectional | Port 1 bit 3 with alternate functions ADC_CH13, I2C0_SCL and STADC (external start ADC trigger). |
| 13 | P2.4 | bidirectional | Port 2 bit 4 with alternate functions ADC_CH12 and T0 (external count input to Timer/Counter 0 or its toggle output). |
| 14 | P2.3 | bidirectional | Port 2 bit 3 with alternate functions ADC_CH11, PWM1_CH0, UART4_TXD and SC2_CLK. |
| 15 | P2.2 | bidirectional | Port 2 bit 2 with alternate functions ADC_CH10, PWM1_CH1, UART4_RXD and SC2_DAT. |
| 16 | P2.1 | bidirectional | Port 2 bit 1 with alternate functions ADC_CH9 and PWM2_CH0. |
| 17 | P3.5 | bidirectional | Port 3 bit 5 with alternate function SPI0_SS (SPI0 slave select input). |
| 18 | P3.1 | bidirectional | Port 3 bit 1 with alternate function PWM2_CH1 (PWM2 output channel 1). |
| 19 | P3.2 | bidirectional | Port 3 bit 2 with alternate function PWM3_CH0 (PWM3 output channel 0). |
| 20 | P1.2 | bidirectional | Port 1 bit 2 with alternate functions PWM0_CH0, PWM1_CH0, IC0, UART3_TXD and SC1_CLK. |
| 21 | P1.1 | bidirectional | Port 1 bit 1 with alternate functions ADC_CH7, PWM0_CH1, PWM1_CH1, IC1, UART3_RXD, SC1_DAT and CLKO (system clock output). |
| 22 | P1.0 | bidirectional | Port 1 bit 0 with alternate functions PWM0_CH2, PWM2_CH0, IC2, SPI0_CLK and UART1_TXD. |
| 23 | P0.0 | bidirectional | Port 0 bit 0 with alternate functions PWM0_CH3, PWM2_CH1, IC3, SPI0_MOSI, UART1_RXD, T1, and XT1_IN/OSCIN (external 4~24 MHz crystal input). |
| 24 | P0.1 | bidirectional | Port 0 bit 1 with alternate functions PWM0_CH4, PWM3_CH0, IC4, SPI0_MISO and XT1_OUT (external 4~24 MHz crystal output). |
| 25 | P3.3 | bidirectional | Port 3 bit 3 with alternate functions PWM0_CH0, CLK_OUT (system clock output) and PWM0_Brake (PWM0 fault brake input). |
| 26 | P0.2 | bidirectional | Port 0 bit 2 with alternate functions I2C0_SCL, UART1_RXD and ICE_CLK (ICE/ICP clock input). |
| 27 | P0.3 | bidirectional | Port 0 bit 3 with alternate functions ADC_CH6, PWM0_CH5, PWM3_CH1, IC5, UART2_TXD and SC0_CLK. |
| 28 | P0.4 | bidirectional | Port 0 bit 4 with alternate functions ADC_CH5, PWM0_CH3, PWM2_CH1, IC3, UART2_RXD, SC0_DAT and STADC (external start ADC trigger). |
| 29 | P0.5 | bidirectional | Port 0 bit 5 with alternate functions ADC_CH4, PWM0_CH2, PWM2_CH0, IC6, UART3_TXD, SC1_CLK and T0. |
| 30 | P0.6 | bidirectional | Port 0 bit 6 with alternate functions ADC_CH3 and UART0_TXD (UART0 transmit data output). |
| 31 | P0.7 | bidirectional | Port 0 bit 7 with alternate functions ADC_CH2 and UART0_RXD. |
| 32 | P3.4 | bidirectional | Port 3 bit 4 with alternate functions PWM3_CH1, UART3_RXD and SC1_DAT. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nuvoton Tech |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Temperature (operating ambient) | TA | -40 |  | 105 | ℃ |  | 51 |
| Operation voltage | VDD | 2.4 |  | 5.5 | V |  | 51 |
| Band-gap voltage | VBG | 1.17 | 1.22 | 1.3 | V | TA = 25 °C | 51 |
| Band-gap voltage | VBG | 1.14 |  | 1.33 | V | TA = -40°C ~105 °C | 51 |
| Normal run mode supply current, 24 MHz HIRC | IDD_RUN |  | 3.6 | 4.8 | mA | @5.5V; executed from Flash, all peripherals disable; max at TA = 105 °C column | 52 |
| Normal run mode supply current, 16 MHz HIRC | IDD_RUN |  | 3.3 | 4.6 | mA | @5.5V; executed from Flash, all peripherals disable; max at TA = 105 °C column | 52 |
| Normal run mode supply current, 10 kHz LIRC | IDD_RUN |  | 0.3 | 2.33 | mA | 10 kHz (LIRC); executed from Flash, all peripherals disable; max at TA = 105 °C column | 52 |
| Idle mode supply current, 24 MHz HIRC | IDD_IDLE |  | 2.8 | 3.8 | mA | @5.5V; executed from Flash, all peripherals disable; max at TA = 105 °C column | 53 |
| Idle mode supply current, 16 MHz HIRC | IDD_IDLE |  | 2.2 | 3.2 | mA | @5.5V; executed from Flash, all peripherals disable; max at TA = 105 °C column | 53 |
| Idle mode supply current, 10 kHz LIRC | IDD_IDLE |  | 0.3 | 2.3 | mA | 10 kHz (LIRC); executed from Flash, all peripherals disable; max at TA = 105 °C column | 53 |
| Power-down mode supply current, all peripherals disabled | IDD_PD |  | 6.5 | 55 | µA | @5.5V; typ at TA = 25 °C; max at TA = 105 °C | 53 |
| Power-down mode supply current, LVR enabled, other peripherals disabled | IDD_PD |  | 7.5 | 57 | µA | typ at TA = 25 °C; max at TA = 105 °C | 53 |
| Power-down mode supply current, LVR and BOD enabled, other peripherals disabled | IDD_PD |  | 180 | 292 | µA | typ at TA = 25 °C; max at TA = 105 °C | 53 |
| Wakeup from IDLE mode | tWU_IDLE |  | 5 | 6 | cycles | Measured with 16 MHz HIRC | 54 |
| Wakeup from power-down mode, Fsys = HIRC @16 MHz | tWU_NPD |  |  | 30 | µs | Fsys = HIRC @16MHz | 54 |
| Wakeup from power-down mode, Fsys = HIRC @24 MHz | tWU_NPD |  |  | 30 | µs | Fsys = HIRC @24MHz | 54 |
| Input leakage current | ILK | -1 |  | 1 | µA | VSS < VIN < VDD, open-drain or input only mode | 55 |
| Source current for quasi-bidirectional mode and high level | ISR | -7.4 |  | -7.5 | µA | VDD = 5.5 V, VIN = (VDD-0.4) V | 56 |
| Source current for quasi-bidirectional mode and high level | ISR | -7.3 |  | -7.5 | µA | VDD = 3.3 V, VIN = (VDD-0.4) V | 56 |
| Source current for quasi-bidirectional mode and high level | ISR | -57.2 |  | -58.3 | µA | VDD = 5.5 V, VIN = 2.4 V | 56 |
| Source current for push-pull mode and high level | ISR | -9 |  | -9.6 | mA | VDD = 5.5 V, VIN = (VDD-0.4) V | 56 |
| Source current for push-pull mode and high level | ISR | -6 |  | -6.6 | mA | VDD = 3.3 V, VIN = (VDD-0.4) V | 56 |
| Source current for push-pull mode and high level | ISR | -4.2 |  | -4.9 | mA | VDD = 2.7 V, VIN = (VDD-0.4) V | 56 |
| Source current for push-pull mode and high level | ISR | -18 |  | -20 | mA | VDD = 5.5 V, VIN = 2.4 V | 56 |
| Sink current for push-pull mode and low level | ISK | 18 |  | 20 | mA | VDD = 5.5 V, VIN = 0.4 V | 56 |
| Sink current for push-pull mode and low level | ISK | 16 |  | 18 | mA | VDD = 3.3 V, VIN = 0.4 V | 56 |
| Sink current for push-pull mode and low level | ISK | 9.7 |  | 11 | mA | VDD = 2.4 V, VIN = 0.4 V | 56 |
| Internal nRESET pull-up resistor | RRST | 45 |  | 60 | KΩ | VDD = 5.5 V | 57 |
| Internal nRESET pull-up resistor | RRST | 45 |  | 65 | KΩ | VDD = 2.4 V | 57 |
| nRESET input response time, power-down mode | tFR | 10 |  | 25 | µs | Power down mode | 57 |
| Frequency drift over temperature and voltage, 16 MHz HIRC |  | -1 |  | 1 | % | TA = 25 °C, VDD = 3.3V | 58 |
| Frequency drift over temperature and voltage, 16 MHz HIRC |  | -2 |  | 2 | % | TA = 25 °C, VDD = 3.3V | 58 |
| Frequency drift over temperature and voltage, 16 MHz HIRC |  | -4 |  | 4 | % | TA = -20 °C ~ +105 °C, VDD = 2.4 ~ 5.5V | 58 |
| Operating current, 16 MHz HIRC | IHRC |  | 490 | 550 | µA | Based on reload value | 58 |
| Stable time, 16 MHz HIRC | TS |  | 3 | 5 | µs | TA = -40 °C ~ +105 °C, VDD = 2.4 ~ 5.5V | 58 |
| Frequency drift over temperature and voltage, 24 MHz HIRC |  | -1 |  | 1 | % | TA = 25 °C, VDD = 3.3V | 59 |
| Frequency drift over temperature and voltage, 24 MHz HIRC |  | -2 |  | 2 | % | TA = -20 °C ~ +85 °C, VDD = 2.4 ~ 5.5V | 59 |
| Frequency drift over temperature and voltage, 24 MHz HIRC |  | -4 |  | 4 | % | TA = -40 °C ~ +105 °C, VDD = 2.4 ~ 5.5V | 59 |
| External crystal/resonator oscillator frequency | fHXT | 4 |  | 24 | MHz |  | 60 |
| HXT duty cycle | DuHXT | 40 |  | 60 | % |  | 60 |
| External user clock source frequency | fHXT_ext | 4 |  | 24 | MHz |  | 61 |
| Clock high time | tCHCX | 8 |  |  | ns |  | 61 |
| Clock low time | tCLCX | 8 |  |  | ns |  | 61 |
| Clock rise time | tCLCH |  |  | 10 | ns | Low (10%) to high level (90%) | 61 |
| Clock fall time | tCHCL |  |  | 10 | ns | High (90%) to low level (10%) | 61 |
| Frequency drift over temperature and voltage, 10 kHz LIRC |  | -10 |  | 10 | % | TA = 25 °C, VDD = 5V | 62 |
| Frequency drift over temperature and voltage, 10 kHz LIRC |  | -35 |  | 35 | % | TA = -40 ~ 105 °C, without software calibration | 62 |
| DC power supply | VDD-VSS | -0.3 |  | 6.5 | V |  | 68 |
| Maximum current into VDD | ΣIDD |  |  | 200 | mA |  | 68 |
| Maximum current out of VSS | ΣISS |  |  | 200 | mA |  | 68 |
| Maximum current sunk by a I/O pin | IIO |  |  | 22 | mA |  | 68 |
| Maximum current sourced by a I/O pin | IIO |  |  | 10 | mA |  | 68 |
| Maximum current sunk by total I/O pins |  |  |  | 100 | mA |  | 68 |
| Maximum current sourced by total I/O pins |  |  |  | 100 | mA |  | 68 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 69 |
| Storage temperature | TST | -65 |  | 150 | °C |  | 69 |

## CAD (KiCad official)

- Symbol: `MS51PC0AE`
- Footprint: `Package_QFP:LQFP-32_7x7mm_P0.8mm`
- 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files: `ms51pc0ae-etched.step` / `ms51pc0ae-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ms51pc0ae.step` / `ms51pc0ae.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nuvoton Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590228088962920448) (80 pp, sha256 `3ef54b54d90b3470`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ms51pc0ae-datasheet.pdf)