component
MS51BA9AE
Public Made by Adomby adom
Nuvoton Tech Microcontroller Units (MCUs/MPUs/SOCs), MSOP-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMS51BA9AE
Nuvoton Tech · Microcontroller Units (MCUs/MPUs/SOCs) · MSOP-10(3x3)
MS51BA9AE from Nuvoton Tech, in a MSOP-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.6 | bidirectional | Port 0 bit 6 GPIO, multiplexed with ADC_CH3 (ADC input channel 3) and UART0_TXD (serial port 0 transmit data output). |
| 2 | nRESET | input | nRESET is a Schmitt trigger active-low hardware reset input with internal pull-up (10 kΩ pull-up and 10 uF capacitor recommended), also usable as P2.0 input when RPD (CONFIG0.2) is 0 and as UART0_RXD receive input. |
| 3 | VSS | power_in | Ground potential. |
| 4 | P1.6 | bidirectional | Port 1 bit 6 GPIO, multiplexed with ICE_DAT (ICP/ICE data input or output, 100 kΩ pull-up recommended), UART1_TXD and remappable [I2C0_SDA]. |
| 5 | VDD | power_in | Supply voltage VDD for operation. |
| 6 | P0.1 | bidirectional | Port 0 bit 1 GPIO, multiplexed with ADC_CH7, PWM0_CH4, SPI0_MISO, IC4 and CLKO (clock output). |
| 7 | P0.2 | bidirectional | Port 0 bit 2 GPIO, multiplexed with ICE_CLK (ICP clock input, 100 kΩ pull-up recommended), PWM0_CH0, UART1_RXD, IC0 and remappable [I2C0_SCL]. |
| 8 | P0.3 | bidirectional | Port 0 bit 3 GPIO, multiplexed with ADC_CH6, PWM0_CH5, I2C0_SCL, IC5 and remappable [STADC] external ADC start trigger. |
| 9 | P0.4 | bidirectional | Port 0 bit 4 GPIO, multiplexed with ADC_CH5, PWM0_CH3, PWM0_BRAKE fault brake input, I2C0_SDA, IC3 and STADC external ADC start trigger. |
| 10 | P0.5 | bidirectional | Port 0 bit 5 GPIO, multiplexed with ADC_CH4, PWM0_CH2, SPI0_SS slave select input, IC6 and T0 external count input/toggle output of Timer/Counter 0. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nuvoton Tech |
| Package | MSOP-10(3x3) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature | TA | -40 | 105 | ℃ | 36 | ||
| Operation voltage | VDD | 2.4 | 5.5 | V | VDD-VSS = 2.4 ~ 5.5V, TA = 25C, Fsys = 16 MHz | 36 | |
| Band-gap voltage | VBG | 1.17 | 1.22 | 1.3 | V | TA = 25 °C | 36 |
| Band-gap voltage | VBG | 1.14 | 1.33 | V | TA = -40°C ~105 °C | 36 | |
| Normal run current, 24 MHz HIRC | IDD_RUN | 3.6 | 4.2 | mA | 24 MHz(HIRC) @5.5V, TA = 25 °C typ; max at TA = -40 °C | 37 | |
| Normal run current, 16 MHz HIRC | IDD_RUN | 3.3 | 3.4 | mA | 16 MHz (HIRC) @5.5V, TA = 25 °C typ; max at TA = -40 °C | 37 | |
| Normal run current, 10 kHz LIRC | IDD_RUN | 0.3 | 0.32 | mA | 10 kHz (LIRC), max at TA = -40 °C | 37 | |
| Idle current, 24 MHz HIRC | IDD_IDLE | 2.8 | 2.9 | mA | 24 MHz(HIRC) @5.5V, TA = 25 °C | 38 | |
| Idle current, 16 MHz HIRC | IDD_IDLE | 2.2 | 2.5 | mA | 16 MHz (HIRC) @5.5V, TA = 25 °C | 38 | |
| Power down current | IDD_PD | 6.5 | 6.2 | µA | Power down mode, all peripherals disable @5.5V; max column TA = -40 °C | 38 | |
| Power down current, TA=105C | IDD_PD | 55 | µA | Power down mode, all peripherals disable, TA = 105 °C | 38 | ||
| Wakeup from IDLE mode | tWU_IDLE | 5 | 6 | cycles | 16 MHz HIRC | 39 | |
| Wakeup from Power down mode | tWU_NPD | 30 | µs | Fsys = HIRC @16MHz | 39 | ||
| Input low voltage (TTL) | VIL | -0.3 | 0.2 | V | min VSS-0.3, max 0.2VDD-0.1 | 40 | |
| Input low voltage | VIL1 | 0 | 0.3 | V | max 0.3*VDD | 40 | |
| Input high voltage | VIH | 0.9 | 0.3 | V | min 0.2VDD+0.9, max VDD+0.3 | 40 | |
| Input high voltage (Schmitt and Xin) | VIH1 | 0.7 | 1 | V | min 0.7*VDD, max VDD | 40 | |
| Input leakage current | ILK | -1 | 1 | µA | VSS < VIN < VDD, Open-drain or input only mode | 40 | |
| Source current push-pull high | ISR | -9 | -9.6 | mA | VDD = 5.5 V, VIN =(VDD-0.4) V | 41 | |
| Source current push-pull high | ISR | -6 | -6.6 | mA | VDD = 3.3 V, VIN =(VDD-0.4) V | 41 | |
| Sink current push-pull low | ISK | 18 | 20 | mA | VDD = 5.5 V, VIN = 0.4 V | 41 | |
| Sink current push-pull low | ISK | 16 | 18 | mA | VDD = 3.3 V, VIN = 0.4 V | 41 | |
| Sink current push-pull low | ISK | 9.7 | 11 | mA | VDD = 2.4 V, VIN = 0.4 V | 41 | |
| I/O pin capacitance | CIO | 5 | pF | 41 | |||
| nRESET negative going threshold | VILR | 0.3 | V | 0.3*VDD | 42 | ||
| nRESET positive going threshold | VIHR | 0.7 | V | 0.7*VDD | 42 | ||
| Internal nRESET pull up resistor | RRST | 45 | 60 | KΩ | VDD = 5.5 V | 42 | |
| Internal nRESET pull up resistor | RRST | 45 | 65 | KΩ | VDD = 2.4 V | 42 | |
| HIRC frequency drift | FHRC | -1 | 1 | % | TA = 25 °C, VDD = 3.3V | 43 | |
| HIRC frequency drift | FHRC | -2 | 2 | % | TA = -20C ~ +105 °C, VDD = 2.4 ~ 5.5V | 43 | |
| HIRC frequency drift | FHRC | -4 | 4 | % | TA = -40C ~ -20 °C, VDD = 2.4 ~ 5.5V | 43 | |
| HIRC operating current | IHRC | 490 | 550 | µA | 43 | ||
| HIRC stable time | TS | 3 | 5 | µs | TA = -40C ~ +105 °C, VDD = 2.4 ~ 5.5V | 43 | |
| LIRC frequency drift | FLRC | -10 | 10 | % | TA = 25 °C, VDD = 5V | 46 | |
| LIRC frequency drift | FLRC | -35 | 35 | % | TA=-40~105°C Without software calibration | 46 | |
| LIRC operating current | ILRC | 0.85 | 1 | µA | VDD = 3.3V | 46 | |
| POR reset voltage | VPOR | 1 | 1.15 | 1.3 | V | 48 | |
| LVR reset voltage | VLVR | 1.7 | 2 | 2.4 | V | 48 | |
| BOD brown-out detect voltage | VBOD | 4.25 | 4.4 | 4.55 | V | BOV[1:0] = [0,0] | 48 |
| BOD brown-out detect voltage | VBOD | 3.55 | 3.7 | 3.85 | V | BOV[1:0] = [0,1] | 48 |
| BOD brown-out detect voltage | VBOD | 2.6 | 2.7 | 2.8 | V | BOV[1:0] = [1,0] | 48 |
| BOD brown-out detect voltage | VBOD | 2.1 | 2.2 | 2.35 | V | BOV[1:0] = [1,1] | 48 |
| Flash supply voltage | VFLA | 1.62 | 1.8 | 1.98 | V | TA = 25℃ | 52 |
| Flash endurance | NENDUR | 100000 | cycles | TJ = -40℃~125℃ | 52 | ||
| DC power supply | VDD-VSS | -0.3 | 6.5 | V | 53 | ||
| Input voltage on I/O | VIN | -0.3 | 5.5 | V | min VSS-0.3 | 53 | |
| Maximum current into VDD | ΣIDD | 150 | mA | 53 | |||
| Maximum current out of VSS | ΣISS | 150 | mA | 53 | |||
| Maximum current sunk by a I/O pin | IIO | 22 | mA | 53 | |||
| Maximum current sourced by a I/O pin | IIO | 10 | mA | 53 | |||
| Operating junction temperature | TJ | -40 | 125 | ℃ | 54 | ||
| Storage temperature | TST | -65 | 150 | ℃ | 54 | ||
| Thermal resistance junction-ambient, 10-pin MSOP (3x3 mm) | θJA | 160 | ℃/Watt | 54 | |||
| ESD human body model | VHBM | -8000 | 8000 | V | 55 | ||
| ESD charge device model | VCDM | -1000 | 1000 | V | 55 | ||
| Pin current for latch-up | LU | -400 | 400 | mA | 55 |
CAD (KiCad official)
- Symbol:
MS51BA9AE - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10(3x3) (KiCad packages3D, STEP)
- 3D model files:
ms51ba9ae-etched.step/ms51ba9ae-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ms51ba9ae.step/ms51ba9ae.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nuvoton Tech datasheet (62 pp, sha256
72116ab91a69ab18, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).