component
MPX2002GY-Z
Public Made by Adomby adom
Monolithic Power Systems AC-DC Controllers And Regulators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MPX2002GY-Z
Monolithic Power Systems · AC-DC Controllers And Regulators · SOIC-16
MPX2002GY-Z from Monolithic Power Systems, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HV | input | High-voltage pin with an internal current source (650V rated) for primary IC start-up and normal operation, sampling input voltage for brown-in/brownout protection and line compensation of primary peak current. |
| 2 | NC | unconnected | No connection. |
| 3 | PEP | input | External protection input on the primary IC for primary MOSFET OTP and auxiliary-winding OVP, with an internal current source for direct connection to the external protection circuit. |
| 4 | PGND | power_in | Ground of the primary-side IC. |
| 5 | VCC | power_in | Power supply for the primary IC (9.5V to 24V recommended) that indirectly senses VOUT for over-voltage protection. |
| 6 | PDRV | output | Output drive for the primary-side external power MOSFET. |
| 7 | CS | input | Primary MOSFET current sense for peak current mode regulation and SCP, with over-power compensation based on HV voltage. |
| 8 | PGND | power_in | Ground of the primary-side IC. |
| 9 | SDRV | output | Output drive for the secondary-side external power MOSFET. |
| 10 | SRD | bidirectional | Voltage-sense drain of the synchronous rectifier MOSFET (-1V to +150V) that controls SR drive and QR operation and can also supply power to VDD. |
| 11 | SGND | power_in | Ground of the secondary side IC. |
| 12 | COMP | passive | Internal error amplifier output for output voltage regulation, connects to a compensation network and can be monitored for secondary overload protection. |
| 13 | VDD | power_in | Power supply for the secondary IC operation (4.8V to 30V recommended). |
| 14 | FB | input | Feedback for constant voltage regulation from a resistor divider sensing output voltage, also reused for output OVP and OLP. |
| 15 | IS | input | Output current sense via a current-sense resistor in the output loop, providing overload protection and cable drop compensation. |
| 16 | SGND | power_in | Ground of the secondary side IC. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | SOIC-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| VCC to PGND (operating) | VCC | 9.5 | 24 | V | 5 | ||
| VDD to SGND (operating) | VDD | 4.8 | 30 | V | 5 | ||
| HV to PGND | HV | -0.3 | 650 | V | 5 | ||
| SRD to SGND | SRD | -1 | 150 | V | 5 | ||
| VCC to PGND | VCC | -0.3 | 35 | V | 5 | ||
| PDRV to PGND | PDRV | -0.3 | 16 | V | 5 | ||
| SDRV to SGND | SDRV | -0.3 | 16 | V | 5 | ||
| VDD to SGND | VDD | -0.3 | 35 | V | 5 | ||
| CS, PEP to PGND | -0.3 | 6.5 | V | 5 | |||
| COMP, FB, IS to SGND | -0.3 | 6.5 | V | 5 | |||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Storage temperature | -60 | 150 | °C | 5 | |||
| Thermal resistance junction-ambient SOICW-16 | θJA | 44 | °C/W | JESD51-7, 4-layer PCB | 5 | ||
| Thermal resistance junction-case SOICW-16 | θJC | 24 | °C/W | JESD51-7, 4-layer PCB | 5 | ||
| HV leakage current | IHV-LK | 7 | 11 | µA | VHV = 500VDC | 6 | |
| HV supply current 1 (25°C) | IHV-SP1 | 4.5 | 5.5 | 6.5 | mA | VCC = 12V, VHV = 80V, TJ = 25°C | 6 |
| HV supply current 1 (105°C) | IHV-SP1 | 3.1 | 3.8 | 4.6 | mA | VCC = 12V, VHV = 80V, TJ = 105°C | 6 |
| Brown-in threshold voltage | VHV-ON | 95 | 107 | 120 | V | 6 | |
| Brown-out threshold voltage | VHV-OFF | 85 | 98 | 110 | V | 6 | |
| Delay time for brown-out | tBO | 45 | 55 | 67 | ms | 6 | |
| IHV-SP turn-off voltage | VCC-IOFF | 13 | 14.5 | 16 | V | 6 | |
| Minimum operation voltage | VCC-MIN | 7.3 | 8.3 | 9.3 | V | 6 | |
| VCC-IOFF - VCC-MIN | VCC-STW | 5.2 | 6.2 | 7.2 | V | 6 | |
| Auto-recovery protection level | VCC-AUT | 4.9 | 5.5 | 6.1 | V | 6 | |
| VCC over-voltage protection level | VCC-OVP | 24 | 26 | 28 | V | 6 | |
| Driver voltage clamp level | VCLAMP | 11.5 | 14.5 | 16 | V | CL = 1nF, VCC = 24V | 6 |
| Time to trigger primary OCP | tOCP | 45 | 55 | 68 | ms | 7 | |
| Threshold for SCP | VSCP | 0.595 | 0.635 | 0.675 | V | 7 | |
| Maximum peak current limitation | VIPK-MAX | 0.384 | 0.4 | 0.416 | V | 7 | |
| CS sourcing current | IHVCS | 100 | 126 | 152 | µA | VHV = 375V, VIPK = VIPK-MAX, TJ = 25°C | 7 |
| Detection time for CS short | tSSP | 4 | 5.8 | 7.5 | µs | 7 | |
| Protection trigger threshold | VPEP-T | 0.425 | 0.5 | 0.575 | V | 7 | |
| UVLO falling threshold | VDD-OFF | 4 | 4.25 | 4.5 | V | 8 | |
| UVLO rising threshold | VDD-ON | 4.3 | 4.5 | 4.7 | V | 8 | |
| VDD ready threshold | VDD-RDY | 4.72 | 4.92 | 5.12 | V | 8 | |
| VDD clamp level when charged by SRD | VDD-C | 4.3 | 4.5 | 4.7 | V | 8 | |
| Feedback reference voltage | VREF | 1.21 | 1.22 | 1.23 | V | TJ = 25°C | 8 |
| FBOLP threshold | VFBO | 0.075 | 0.095 | 0.115 | V | VDD > VDD-RDY | 8 |
| OVP threshold | VOVP | 113 | 118 | 123 | % VREF | 8 | |
| SR turn-on threshold | VSR-ON | -50 | -37 | -24 | mV | 8 | |
| Regulated forward voltage | VFWD | 8 | 20 | 32 | mV | 8 | |
| SR turn-off threshold | VSR-OFF | 8 | 18 | 28 | mV | 8 | |
| Threshold for driver open detection | VSGO | -0.52 | -0.47 | -0.42 | V | TJ = 25°C | 8 |
| Blanking for turn-on detection | tSR-ONB | 270 | 400 | 570 | ns | 8 | |
| Turn-off delay | tSR-OFFD | 35 | 62 | ns | CL = 4.7nF | 9 | |
| Minimal on time | tON-MIN | 0.8 | 1.05 | 1.35 | µs | 9 | |
| SDRV driver voltage high level | VDRV-H | 4.1 | 4.3 | 4.6 | V | VDD = VDD-OFF + 0.1V | 9 |
| Driver pull-down resistance | RPULL-DOWN | 0.65 | 1.05 | Ω | CL = 4.7nF, VDD = 12V | 9 | |
| Overload protection threshold | VOLP | 37 | 42 | 47 | mV | 9 | |
| Overload protection delay | tOLP | 55 | 66 | 77 | ms | 9 | |
| Maximum sink current | ISINK | 56 | 86 | 120 | mA | 9 | |
| Maximum source current | ISOURCE | -125 | -88 | -60 | mA | 9 | |
| Maximum COMP voltage | VCOMP-S | 2.25 | 2.38 | 2.51 | V | VDD = 5V | 9 |
| Threshold for max frequency limitation | VFS-MAX | 2.12 | 2.2 | 2.3 | V | 9 | |
| Threshold for burst entry | VBURST | 0.3 | 0.33 | 0.36 | V | 9 | |
| Maximum PFM frequency | fS-MAX | 82 | 85 | 89 | kHz | TJ = 25°C | 9 |
| Isolation voltage | VISO | 3.75 | kVRMS | 50Hz/60Hz | 6 | ||
| HV breakdown voltage | VHV-BD | 650 | V | TJ = 25°C | 6 |
CAD (KiCad official)
- Symbol:
MPX2002GY-Z - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mpx2002gy-z-etched.step/mpx2002gy-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mpx2002gy-z.step/mpx2002gy-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems datasheet (37 pp, sha256
16e504845bc3d94e, retrieved 2026-10-31, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MPX2002GY-Z
**Monolithic Power Systems** · AC-DC Controllers And Regulators · SOIC-16
MPX2002GY-Z from Monolithic Power Systems, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HV | input | High-voltage pin with an internal current source (650V rated) for primary IC start-up and normal operation, sampling input voltage for brown-in/brownout protection and line compensation of primary peak current. |
| 2 | NC | unconnected | No connection. |
| 3 | PEP | input | External protection input on the primary IC for primary MOSFET OTP and auxiliary-winding OVP, with an internal current source for direct connection to the external protection circuit. |
| 4 | PGND | power_in | Ground of the primary-side IC. |
| 5 | VCC | power_in | Power supply for the primary IC (9.5V to 24V recommended) that indirectly senses VOUT for over-voltage protection. |
| 6 | PDRV | output | Output drive for the primary-side external power MOSFET. |
| 7 | CS | input | Primary MOSFET current sense for peak current mode regulation and SCP, with over-power compensation based on HV voltage. |
| 8 | PGND | power_in | Ground of the primary-side IC. |
| 9 | SDRV | output | Output drive for the secondary-side external power MOSFET. |
| 10 | SRD | bidirectional | Voltage-sense drain of the synchronous rectifier MOSFET (-1V to +150V) that controls SR drive and QR operation and can also supply power to VDD. |
| 11 | SGND | power_in | Ground of the secondary side IC. |
| 12 | COMP | passive | Internal error amplifier output for output voltage regulation, connects to a compensation network and can be monitored for secondary overload protection. |
| 13 | VDD | power_in | Power supply for the secondary IC operation (4.8V to 30V recommended). |
| 14 | FB | input | Feedback for constant voltage regulation from a resistor divider sensing output voltage, also reused for output OVP and OLP. |
| 15 | IS | input | Output current sense via a current-sense resistor in the output loop, providing overload protection and cable drop compensation. |
| 16 | SGND | power_in | Ground of the secondary side IC. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | SOIC-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating junction temperature | TJ | -40 | | 125 | °C | | 5 |
| VCC to PGND (operating) | VCC | 9.5 | | 24 | V | | 5 |
| VDD to SGND (operating) | VDD | 4.8 | | 30 | V | | 5 |
| HV to PGND | HV | -0.3 | | 650 | V | | 5 |
| SRD to SGND | SRD | -1 | | 150 | V | | 5 |
| VCC to PGND | VCC | -0.3 | | 35 | V | | 5 |
| PDRV to PGND | PDRV | -0.3 | | 16 | V | | 5 |
| SDRV to SGND | SDRV | -0.3 | | 16 | V | | 5 |
| VDD to SGND | VDD | -0.3 | | 35 | V | | 5 |
| CS, PEP to PGND | | -0.3 | | 6.5 | V | | 5 |
| COMP, FB, IS to SGND | | -0.3 | | 6.5 | V | | 5 |
| Junction temperature | TJ | | | 150 | °C | | 5 |
| Storage temperature | | -60 | | 150 | °C | | 5 |
| Thermal resistance junction-ambient SOICW-16 | θJA | | 44 | | °C/W | JESD51-7, 4-layer PCB | 5 |
| Thermal resistance junction-case SOICW-16 | θJC | | 24 | | °C/W | JESD51-7, 4-layer PCB | 5 |
| HV leakage current | IHV-LK | | 7 | 11 | µA | VHV = 500VDC | 6 |
| HV supply current 1 (25°C) | IHV-SP1 | 4.5 | 5.5 | 6.5 | mA | VCC = 12V, VHV = 80V, TJ = 25°C | 6 |
| HV supply current 1 (105°C) | IHV-SP1 | 3.1 | 3.8 | 4.6 | mA | VCC = 12V, VHV = 80V, TJ = 105°C | 6 |
| Brown-in threshold voltage | VHV-ON | 95 | 107 | 120 | V | | 6 |
| Brown-out threshold voltage | VHV-OFF | 85 | 98 | 110 | V | | 6 |
| Delay time for brown-out | tBO | 45 | 55 | 67 | ms | | 6 |
| IHV-SP turn-off voltage | VCC-IOFF | 13 | 14.5 | 16 | V | | 6 |
| Minimum operation voltage | VCC-MIN | 7.3 | 8.3 | 9.3 | V | | 6 |
| VCC-IOFF - VCC-MIN | VCC-STW | 5.2 | 6.2 | 7.2 | V | | 6 |
| Auto-recovery protection level | VCC-AUT | 4.9 | 5.5 | 6.1 | V | | 6 |
| VCC over-voltage protection level | VCC-OVP | 24 | 26 | 28 | V | | 6 |
| Driver voltage clamp level | VCLAMP | 11.5 | 14.5 | 16 | V | CL = 1nF, VCC = 24V | 6 |
| Time to trigger primary OCP | tOCP | 45 | 55 | 68 | ms | | 7 |
| Threshold for SCP | VSCP | 0.595 | 0.635 | 0.675 | V | | 7 |
| Maximum peak current limitation | VIPK-MAX | 0.384 | 0.4 | 0.416 | V | | 7 |
| CS sourcing current | IHVCS | 100 | 126 | 152 | µA | VHV = 375V, VIPK = VIPK-MAX, TJ = 25°C | 7 |
| Detection time for CS short | tSSP | 4 | 5.8 | 7.5 | µs | | 7 |
| Protection trigger threshold | VPEP-T | 0.425 | 0.5 | 0.575 | V | | 7 |
| UVLO falling threshold | VDD-OFF | 4 | 4.25 | 4.5 | V | | 8 |
| UVLO rising threshold | VDD-ON | 4.3 | 4.5 | 4.7 | V | | 8 |
| VDD ready threshold | VDD-RDY | 4.72 | 4.92 | 5.12 | V | | 8 |
| VDD clamp level when charged by SRD | VDD-C | 4.3 | 4.5 | 4.7 | V | | 8 |
| Feedback reference voltage | VREF | 1.21 | 1.22 | 1.23 | V | TJ = 25°C | 8 |
| FBOLP threshold | VFBO | 0.075 | 0.095 | 0.115 | V | VDD > VDD-RDY | 8 |
| OVP threshold | VOVP | 113 | 118 | 123 | % VREF | | 8 |
| SR turn-on threshold | VSR-ON | -50 | -37 | -24 | mV | | 8 |
| Regulated forward voltage | VFWD | 8 | 20 | 32 | mV | | 8 |
| SR turn-off threshold | VSR-OFF | 8 | 18 | 28 | mV | | 8 |
| Threshold for driver open detection | VSGO | -0.52 | -0.47 | -0.42 | V | TJ = 25°C | 8 |
| Blanking for turn-on detection | tSR-ONB | 270 | 400 | 570 | ns | | 8 |
| Turn-off delay | tSR-OFFD | 35 | | 62 | ns | CL = 4.7nF | 9 |
| Minimal on time | tON-MIN | 0.8 | 1.05 | 1.35 | µs | | 9 |
| SDRV driver voltage high level | VDRV-H | 4.1 | 4.3 | 4.6 | V | VDD = VDD-OFF + 0.1V | 9 |
| Driver pull-down resistance | RPULL-DOWN | | 0.65 | 1.05 | Ω | CL = 4.7nF, VDD = 12V | 9 |
| Overload protection threshold | VOLP | 37 | 42 | 47 | mV | | 9 |
| Overload protection delay | tOLP | 55 | 66 | 77 | ms | | 9 |
| Maximum sink current | ISINK | 56 | 86 | 120 | mA | | 9 |
| Maximum source current | ISOURCE | -125 | -88 | -60 | mA | | 9 |
| Maximum COMP voltage | VCOMP-S | 2.25 | 2.38 | 2.51 | V | VDD = 5V | 9 |
| Threshold for max frequency limitation | VFS-MAX | 2.12 | 2.2 | 2.3 | V | | 9 |
| Threshold for burst entry | VBURST | 0.3 | 0.33 | 0.36 | V | | 9 |
| Maximum PFM frequency | fS-MAX | 82 | 85 | 89 | kHz | TJ = 25°C | 9 |
| Isolation voltage | VISO | 3.75 | | | kVRMS | 50Hz/60Hz | 6 |
| HV breakdown voltage | VHV-BD | 650 | | | V | TJ = 25°C | 6 |
## CAD (KiCad official)
- Symbol: `MPX2002GY-Z`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `mpx2002gy-z-etched.step` / `mpx2002gy-z-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mpx2002gy-z.step` / `mpx2002gy-z.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Monolithic Power Systems datasheet](docs/mpx2002gy-z-datasheet.pdf) (37 pp, sha256 `16e504845bc3d94e`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mpx2002gy-z-datasheet.pdf)