# MPQ6610GS-AEC1-Z

**Monolithic Power Systems** · Brushed DC Motor Drivers · SOIC-8

MPQ6610GS-AEC1-Z from Monolithic Power Systems, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | passive | Bootstrap pin; connect a 100nF capacitor between BST and OUT, with BST rated from VIN to VIN + 5.7V. |
| 2 | VIN | power_in | Input supply voltage with a 4V to 55V recommended range for the SOIC-8 package; decouple VIN to GND with a minimum 100nF ceramic capacitor. |
| 3 | OUT | output | Half-bridge output terminal; OUT voltage absolute maximum is -0.7V to +65V. |
| 4 | GND | power_in | System ground connection. |
| 5 | nFAULT | output | Open-drain fault indication output that is driven logic low on over-current protection, over-temperature protection, or open-load faults, and requires an external pull-up resistor. |
| 6 | ISET | output | Current configuration resistor connection; a resistor from ISET to ground sets the current limit and ISET voltage scaling, with the current trip voltage at 1.5V typical. |
| 7 | IN | input | H-bridge input; drive IN high to drive the output high, and the pin is pulled down with an internal resistor (530kΩ typical). |
| 8 | EN | input | H-bridge enable input; drive EN high to enable the half-bridge driver, and the pin is pulled down with an internal resistor (530kΩ typical). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage | VIN | 4 |  | 55 | V | SOIC-8 package | 4 |
| Quiescent current | IQ |  | 1.3 | 5 | mA | VIN = 24V, EN = 0, no load current | 4 |
| Output on resistance HS | RHS |  | 100 | 120 | mΩ | VIN = 24V, IOUT = 1A, TJ = 25°C | 4 |
| Output on resistance HS | RHS |  | 120 | 200 | mΩ | VIN = 24V, IOUT = 1A, TJ = 125°C | 4 |
| Output on resistance LS | RLS |  | 120 | 150 | mΩ | VIN = 24V, IOUT = 1A, TJ = 25°C | 4 |
| Output on resistance LS | RLS |  | 150 | 256 | mΩ | VIN = 24V, IOUT = 1A, TJ = 125°C | 4 |
| Input logic low threshold | VIL |  |  | 0.8 | V |  | 4 |
| Input logic high threshold | VIH | 2 |  |  | V |  | 4 |
| Logic input current IIN(H) | IIN(H) |  | 6 | 14 | µA | VIH = 5V | 4 |
| Logic input current IIN(L) | IIN(L) |  |  | 4 | µA | VIL = 0.8V | 4 |
| nFault output low voltage | VOL |  |  | 0.8 | V | IOUT = 5mA | 4 |
| Output high leakage current | IOH |  |  | 1 | µA | VOUT = 3.3V | 4 |
| OVP rising threshold | VOV_RISE | 55 |  | 65 | V |  | 4 |
| Open-load detection threshold | VOLD | 1 |  | 1.5 | V | OUT = low | 4 |
| Open-load detection threshold | VOLD | 21.5 |  | 23.2 | V | OUT = high, VIN = 24V | 4 |
| ISET current HS source | IISET | 69 | 90 | 118 | µA/A | HS source, IOUT = 1A | 5 |
| ISET current HS sink | IISET | 82 | 102 | 131 | µA/A | HS sink, IOUT = 1A | 5 |
| ISET current LS source | IISET | 83 | 104 | 130 | µA/A | LS source, IOUT = 1A | 5 |
| ISET current LS sink | IISET | 82 | 103 | 129 | µA/A | LS sink, IOUT = 1A | 5 |
| Current trip voltage | VITRIP | 1.4 | 1.5 | 1.6 | V | At ISET pin | 5 |
| Supply voltage (SOIC) | VIN | 4 |  | 55 | V | SOIC package | 3 |
| Output current | IOUT | -3 |  | 3 | A |  | 3 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 3 |
| Supply voltage VIN | VIN | -0.3 |  | 65 | V |  | 3 |
| OUT voltage | VOUT | -0.7 |  | 65 | V |  | 3 |
| ISET voltage | ISET | -0.3 |  | 5.5 | V |  | 3 |
| All other pins to GND |  | -0.3 |  | 6.5 | V |  | 3 |
| Continuous power dissipation |  |  |  | 1.302 | W | TA = 25°C, SOIC package | 3 |
| Storage temperature |  | -55 |  | 150 | °C |  | 3 |
| Junction temperature |  |  |  | 150 | °C |  | 3 |
| ESD charged device model |  | -750 |  | 750 | V | CDM | 3 |
| Thermal resistance junction-to-case | θJC |  | 45 |  | °C/W | SOIC package, JESD51-7, 4-layer PCB | 3 |

## CAD (KiCad official)

- Symbol: `MPQ6610GS-AEC1-Z`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `mpq6610gs-aec1-z-etched.step` / `mpq6610gs-aec1-z-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mpq6610gs-aec1-z.step` / `mpq6610gs-aec1-z.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Monolithic Power Systems datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590905480531427328) (16 pp, sha256 `b0a3384ea32c3bab`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mpq6610gs-aec1-z-datasheet.pdf)