component
MPQ5850GJ-AEC1-Z
Public Made by Adomby adom
MONOLITHIC POWER SYSTEMS INC. Global Sourcing Parts, TSOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MPQ5850GJ-AEC1-Z
MONOLITHIC POWER SYSTEMS INC. · Global Sourcing Parts · TSOT-23-8
MPQ5850GJ-AEC1-Z from MONOLITHIC POWER SYSTEMS INC., in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN/UVLO | input | Enable pin that shuts the chip down when pulled below 1V and enables it when pulled above 1.2V, and it must not be left floating. |
| 2 | PG | output | Open-drain power good pin that asserts low when the device is disabled, the reservoir supply is out of regulation, or the fast pull-up path is active for longer than 17μs. |
| 3 | GND | power_in | Ground connection of the device, which must be connected to the board ground plane. |
| 4 | SW | passive | Switch node of the internal boost regulator, with an inductor connected between SW and DRAIN. |
| 5 | RES | power_in | Reservoir supply for the external N-channel MOSFET gate driver, requiring a minimum 1μF ceramic capacitor between RES and DRAIN. |
| 6 | DRAIN | power_in | Drain connection to the external power MOSFET that also supplies the internal circuitry, requiring a minimum 4.7μF capacitor from DRAIN to ground. |
| 7 | GATE | output | Gate connection to the external power MOSFET gate, with 170mA fast pull-up and 430mA fast pull-down current. |
| 8 | SOURCE | input | Source connection to the external power MOSFET source, sensed together with DRAIN to control the gate, with an absolute maximum range of -36V to +42V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MONOLITHIC POWER SYSTEMS INC. |
| Package | TSOT-23-8 |
| Category | Global Sourcing Parts |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain voltage at start-up | VDRAIN_UVLO | 2.8 | 3.2 | V | 5 | ||
| Drain voltage UVLO falling | VDRAIN_UVLO_F | 2.4 | 2.6 | 2.8 | V | 5 | |
| Reservoir UVLO rising | VRES_UVLO | 8 | 11 | 13 | V | 5 | |
| Reservoir UVLO hysteresis | VRES_UVLO_HYS | 0.2 | V | 5 | |||
| Quiescent current in standby | ISHDN | 4 | 10 | μA | VEN = 0V, TJ = 25°C | 5 | |
| Quiescent current in standby | ISHDN | 20 | μA | VEN = 0V, TJ = -40°C to +150°C | 5 | ||
| Quiescent current in steady state | IQ | 30 | 50 | μA | VEN = 2V, in regulation, system input current, TJ = 25°C | 5 | |
| Quiescent current in steady state | IQ | 100 | μA | VEN = 2V, in regulation, system input current, TJ = -40°C to +125°C | 5 | ||
| Quiescent current in steady state | IQ | 200 | μA | VEN = 2V, in regulation, system input current, TJ = 125°C to 150°C | 5 | ||
| Source to drain regulation voltage | VSD | 10 | 20 | 30 | mV | 5 | |
| Source to drain fast pull-up threshold | VSD_FPU | 50 | 75 | 100 | mV | 5 | |
| Source to drain fast pull-down threshold | VSD_FPD | -15 | -4 | 0 | mV | 5 | |
| Drain current | ID | 50 | μA | Gate driver in regulation | 5 | ||
| Source current | IS_R | -1 | mA | VSOURCE = -36V | 5 | ||
| Fast pull up current | IFPU | 170 | mA | VGATE-RES = -7V | 5 | ||
| Fast pull down current | IFPD | 430 | mA | VGATE-SOURCE = 5V | 5 | ||
| Reverse biased gate-source voltage | VGS_RB | 0.01 | 0.3 | V | VSOURCE = -5V, IGATE = 1mA | 5 | |
| Gate turn-on delay time | tON | 1.2 | 2 | μs | Step (VSOURCE - VDRAIN) from -100mV to +3V, VRES-DRAIN = 13V, CGATE-SOURCE = 10nF | 5 | |
| Gate turn-off delay time | tOFF | 1 | 2 | μs | Step (VSOURCE - VDRAIN) from 3V to -100mV, VRES-DRAIN = 13V, CGATE-SOURCE = 10nF | 5 | |
| Gate rising time | tRISING | 300 | ns | Step (VSOURCE - VDRAIN) from -100mV to +3V, VRES-DRAIN = 13V, CGATE-SOURCE = 10nF | 5 | ||
| Gate falling time | tFALLING | 100 | ns | Step (VSOURCE - VDRAIN) from 3V to -100mV, VRES-DRAIN = 13V, CGATE-SOURCE = 10nF | 5 | ||
| Maximum rectification frequency | fMAX | 50 | kHz | VPP = 6V, CGATE-SOURCE = 15nF | 5 | ||
| Maximum rectification frequency | fMAX | 100 | kHz | VPP = 2V, CGATE-SOURCE = 15nF | 5 | ||
| Reservoir regulation voltage | VREG | 10 | 12 | 14 | V | 6 | |
| Reservoir regulation UVLO hysteresis | VREG_UVLO_HYS | 1.2 | V | VREG - VRES_UVLO - VRES_UVLO_HYS | 6 | ||
| Boost current limit | IBOOST | 160 | 220 | 280 | mA | 6 | |
| SW leakage | ISW | 1 | μA | 6 | |||
| Boost power switch on resistance | RSW | 1.5 | 3.5 | Ω | 6 | ||
| Boost rectifier diode voltage drop | VDIODE | 0.9 | V | IDIODE = 220mA | 6 | ||
| Enable threshold rising | VEN | 1 | 1.2 | 1.4 | V | 6 | |
| Enable threshold falling | VEN_F | 0.8 | 1 | 1.2 | V | 6 | |
| Enable hysteresis | VEN_H | 200 | mV | 6 | |||
| Enable leakage | IEN | 1 | μA | VEN = 3V | 6 | ||
| PG output voltage low | VPG_LOW | 0.1 | 0.3 | V | ISINK = 1mA | 6 | |
| Thermal shutdown | TSD | 175 | °C | Derived from bench characterization, not tested in production | 6 | ||
| Thermal shutdown hysteresis | TSD_HYS | 25 | °C | Derived from bench characterization, not tested in production | 6 | ||
| SOURCE, EN/UVLO voltage | VSOURCE, VEN/UVLO | -36 | 42 | V | 4 | ||
| DRAIN voltage | VDRAIN | -0.3 | 42 | V | 4 | ||
| DRAIN - SOURCE voltage | VDRAIN-SOURCE | -2 | 52 | V | 4 | ||
| GATE - SOURCE voltage | VGATE-SOURCE | -0.3 | 13 | V | 4 | ||
| RES voltage | VRES | -0.3 | V | Upper limit is VDRAIN + 13V | 4 | ||
| SW voltage | VSW | -0.3 | 57 | V | 4 | ||
| PG voltage | VPG | -0.3 | 6 | V | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Supply voltage | VIN | 3.3 | 36 | V | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Thermal resistance junction-to-ambient | θJA | 85 | °C/W | JESD51-7, 4-layer PCB | 4 | ||
| Thermal resistance junction-to-case | θJC | 20 | °C/W | JESD51-7, 4-layer PCB | 4 |
CAD (KiCad official)
- Symbol:
MPQ5850GJ-AEC1-Z - Footprint:
Package_TO_SOT_SMD:TSOT-23-8 - 3D model: TSOT-23-8 (KiCad packages3D, STEP)
- 3D model files:
mpq5850gj-aec1-z-etched.step/mpq5850gj-aec1-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mpq5850gj-aec1-z.step/mpq5850gj-aec1-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MONOLITHIC POWER SYSTEMS INC. datasheet (29 pp, sha256
99caec3edd256fd8, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MPQ5850GJ-AEC1-Z
**MONOLITHIC POWER SYSTEMS INC.** · Global Sourcing Parts · TSOT-23-8
MPQ5850GJ-AEC1-Z from MONOLITHIC POWER SYSTEMS INC., in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN/UVLO | input | Enable pin that shuts the chip down when pulled below 1V and enables it when pulled above 1.2V, and it must not be left floating. |
| 2 | PG | output | Open-drain power good pin that asserts low when the device is disabled, the reservoir supply is out of regulation, or the fast pull-up path is active for longer than 17μs. |
| 3 | GND | power_in | Ground connection of the device, which must be connected to the board ground plane. |
| 4 | SW | passive | Switch node of the internal boost regulator, with an inductor connected between SW and DRAIN. |
| 5 | RES | power_in | Reservoir supply for the external N-channel MOSFET gate driver, requiring a minimum 1μF ceramic capacitor between RES and DRAIN. |
| 6 | DRAIN | power_in | Drain connection to the external power MOSFET that also supplies the internal circuitry, requiring a minimum 4.7μF capacitor from DRAIN to ground. |
| 7 | GATE | output | Gate connection to the external power MOSFET gate, with 170mA fast pull-up and 430mA fast pull-down current. |
| 8 | SOURCE | input | Source connection to the external power MOSFET source, sensed together with DRAIN to control the gate, with an absolute maximum range of -36V to +42V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MONOLITHIC POWER SYSTEMS INC. |
| Package | TSOT-23-8 |
| Category | Global Sourcing Parts |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain voltage at start-up | VDRAIN_UVLO | | 2.8 | 3.2 | V | | 5 |
| Drain voltage UVLO falling | VDRAIN_UVLO_F | 2.4 | 2.6 | 2.8 | V | | 5 |
| Reservoir UVLO rising | VRES_UVLO | 8 | 11 | 13 | V | | 5 |
| Reservoir UVLO hysteresis | VRES_UVLO_HYS | | | 0.2 | V | | 5 |
| Quiescent current in standby | ISHDN | | 4 | 10 | μA | VEN = 0V, TJ = 25°C | 5 |
| Quiescent current in standby | ISHDN | | | 20 | μA | VEN = 0V, TJ = -40°C to +150°C | 5 |
| Quiescent current in steady state | IQ | | 30 | 50 | μA | VEN = 2V, in regulation, system input current, TJ = 25°C | 5 |
| Quiescent current in steady state | IQ | | | 100 | μA | VEN = 2V, in regulation, system input current, TJ = -40°C to +125°C | 5 |
| Quiescent current in steady state | IQ | | | 200 | μA | VEN = 2V, in regulation, system input current, TJ = 125°C to 150°C | 5 |
| Source to drain regulation voltage | VSD | 10 | 20 | 30 | mV | | 5 |
| Source to drain fast pull-up threshold | VSD_FPU | 50 | 75 | 100 | mV | | 5 |
| Source to drain fast pull-down threshold | VSD_FPD | -15 | -4 | 0 | mV | | 5 |
| Drain current | ID | | | 50 | μA | Gate driver in regulation | 5 |
| Source current | IS_R | | | -1 | mA | VSOURCE = -36V | 5 |
| Fast pull up current | IFPU | | | 170 | mA | VGATE-RES = -7V | 5 |
| Fast pull down current | IFPD | | | 430 | mA | VGATE-SOURCE = 5V | 5 |
| Reverse biased gate-source voltage | VGS_RB | | 0.01 | 0.3 | V | VSOURCE = -5V, IGATE = 1mA | 5 |
| Gate turn-on delay time | tON | | 1.2 | 2 | μs | Step (VSOURCE - VDRAIN) from -100mV to +3V, VRES-DRAIN = 13V, CGATE-SOURCE = 10nF | 5 |
| Gate turn-off delay time | tOFF | | 1 | 2 | μs | Step (VSOURCE - VDRAIN) from 3V to -100mV, VRES-DRAIN = 13V, CGATE-SOURCE = 10nF | 5 |
| Gate rising time | tRISING | | | 300 | ns | Step (VSOURCE - VDRAIN) from -100mV to +3V, VRES-DRAIN = 13V, CGATE-SOURCE = 10nF | 5 |
| Gate falling time | tFALLING | | | 100 | ns | Step (VSOURCE - VDRAIN) from 3V to -100mV, VRES-DRAIN = 13V, CGATE-SOURCE = 10nF | 5 |
| Maximum rectification frequency | fMAX | | | 50 | kHz | VPP = 6V, CGATE-SOURCE = 15nF | 5 |
| Maximum rectification frequency | fMAX | | | 100 | kHz | VPP = 2V, CGATE-SOURCE = 15nF | 5 |
| Reservoir regulation voltage | VREG | 10 | 12 | 14 | V | | 6 |
| Reservoir regulation UVLO hysteresis | VREG_UVLO_HYS | | | 1.2 | V | VREG - VRES_UVLO - VRES_UVLO_HYS | 6 |
| Boost current limit | IBOOST | 160 | 220 | 280 | mA | | 6 |
| SW leakage | ISW | | | 1 | μA | | 6 |
| Boost power switch on resistance | RSW | | 1.5 | 3.5 | Ω | | 6 |
| Boost rectifier diode voltage drop | VDIODE | | | 0.9 | V | IDIODE = 220mA | 6 |
| Enable threshold rising | VEN | 1 | 1.2 | 1.4 | V | | 6 |
| Enable threshold falling | VEN_F | 0.8 | 1 | 1.2 | V | | 6 |
| Enable hysteresis | VEN_H | | | 200 | mV | | 6 |
| Enable leakage | IEN | | | 1 | μA | VEN = 3V | 6 |
| PG output voltage low | VPG_LOW | | 0.1 | 0.3 | V | ISINK = 1mA | 6 |
| Thermal shutdown | TSD | | | 175 | °C | Derived from bench characterization, not tested in production | 6 |
| Thermal shutdown hysteresis | TSD_HYS | | | 25 | °C | Derived from bench characterization, not tested in production | 6 |
| SOURCE, EN/UVLO voltage | VSOURCE, VEN/UVLO | -36 | | 42 | V | | 4 |
| DRAIN voltage | VDRAIN | -0.3 | | 42 | V | | 4 |
| DRAIN - SOURCE voltage | VDRAIN-SOURCE | -2 | | 52 | V | | 4 |
| GATE - SOURCE voltage | VGATE-SOURCE | -0.3 | | 13 | V | | 4 |
| RES voltage | VRES | -0.3 | | | V | Upper limit is VDRAIN + 13V | 4 |
| SW voltage | VSW | -0.3 | | 57 | V | | 4 |
| PG voltage | VPG | -0.3 | | 6 | V | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Supply voltage | VIN | 3.3 | | 36 | V | | 4 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 4 |
| Thermal resistance junction-to-ambient | θJA | | 85 | | °C/W | JESD51-7, 4-layer PCB | 4 |
| Thermal resistance junction-to-case | θJC | | 20 | | °C/W | JESD51-7, 4-layer PCB | 4 |
## CAD (KiCad official)
- Symbol: `MPQ5850GJ-AEC1-Z`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-8`
- 3D model: TSOT-23-8 (KiCad packages3D, STEP)
- 3D model files: `mpq5850gj-aec1-z-etched.step` / `mpq5850gj-aec1-z-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mpq5850gj-aec1-z.step` / `mpq5850gj-aec1-z.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [MONOLITHIC POWER SYSTEMS INC. datasheet](docs/mpq5850gj-aec1-z-datasheet.pdf) (29 pp, sha256 `99caec3edd256fd8`, retrieved 2026-10-26, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mpq5850gj-aec1-z-datasheet.pdf)