# MPQ4559DN-LF-Z

**Monolithic Power Systems** · DC-DC Converters · SOIC-8-EP

MPQ4559DN-LF-Z from Monolithic Power Systems, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switch node output from the high-side switch; a low VF Schottky rectifier to ground is required and must be placed close to the SW pin to reduce switching spikes. |
| 2 | EN | input | Enable input; pull below the specified threshold to shut down the chip, pull above the threshold or leave floating to enable it. |
| 3 | COMP | passive | Compensation pin, the output of the GM error amplifier, where control loop frequency compensation is applied. |
| 4 | FB | input | Feedback input to the error amplifier; sets the regulator voltage by comparing an external resistive divider tap to the internal 0.8V reference. |
| 5 | GND | power_in | Ground, also the exposed pad; connect close to the output capacitor avoiding high-current switch paths, and connect the exposed pad to the GND plane for optimal thermal performance. |
| 6 | FREQ | passive | Switching frequency program input; connect a resistor from this pin to ground to set the switching frequency. |
| 7 | VIN | power_in | Input supply (3.8V to 55V recommended) powering all internal control circuitry, both BS regulators and the high-side switch; place a decoupling capacitor to ground close to this pin. |
| 8 | BST | passive | Bootstrap positive supply for the internal floating high-side MOSFET driver; connect a bypass capacitor between this pin and SW. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Voltage | VFB | 0.78 | 0.8 | 0.82 | V | 4.5V < VIN < 55V, TJ = 25C | 3 |
| Feedback Voltage | VFB | 0.772 |  | 0.829 | V | 4.5V < VIN < 55V, -40C ≤ TJ ≤ 85C | 3 |
| Feedback Voltage | VFB | 0.766 |  | 0.829 | V | 4.5V < VIN < 55V, -40C ≤ TJ ≤ 125C | 3 |
| Feedback Leakage Current | IFB |  | 0.1 | 1 | μA |  | 3 |
| Upper Switch On Resistance | RDS(ON) | 175 | 250 | 330 | mΩ | VBST, VSW = 5V, TJ = 25C | 3 |
| Upper Switch On Resistance (full temp) | RDS(ON) | 160 |  | 400 | mΩ | VBST, VSW = 5V | 3 |
| Upper Switch Leakage | ISW |  |  | 1 | μA | VEN = 0V, VSW = 0V | 3 |
| Current Limit | ILIM | 1.9 | 2.3 | 4.5 | A | TJ = 25C, Duty Cycle ≤ 60% | 3 |
| Current Limit (full temp) | ILIM | 1.8 |  | 4.7 | A | Duty Cycle ≤ 60% | 3 |
| VIN UVLO Threshold |  | 2.7 | 3 | 3.3 | V | TJ = 25C | 3 |
| VIN UVLO Threshold (full temp) |  | 2.4 | 3 | 3.6 | V |  | 3 |
| Soft-Start Time |  |  | 0.19 | 0.5 | ms | 0V < VFB < 0.8V | 3 |
| Oscillator Frequency | fSW | 0.8 | 1 | 1.2 | MHz | RFREQ = 95kΩ, TJ = 25C | 3 |
| Oscillator Frequency (full temp) | fSW | 0.7 |  | 1.3 | MHz | RFREQ = 95kΩ | 3 |
| Shutdown Supply Current | IS |  | 12 | 20 | µA | VEN < 0.3V | 3 |
| Quiescent Supply Current | IQ |  | 140 | 200 | µA | No load, VFB = 0.9V (no switching) | 3 |
| EN Rising Threshold |  | 1.4 | 1.55 | 1.7 | V | TJ = 25C | 3 |
| EN Rising Threshold (full temp) |  | 1.3 |  | 1.8 | V |  | 3 |
| COMP to Current Sense Transconductance | GCS |  | 5.7 |  | A/V |  | 3 |
| Error Amp Voltage Gain |  |  | 400 |  | V/V |  | 3 |
| Error Amp Transconductance |  |  | 120 |  | µA/V | ICOMP = ±3µA | 3 |
| Error Amp Min Source current |  |  | 10 |  | µA | VFB = 0.7V | 3 |
| Error Amp Min Sink current |  |  | -10 |  | µA | VFB = 0.9V | 3 |
| VIN UVLO Hysteresis |  |  | 0.35 |  | V |  | 3 |
| Thermal Shutdown |  |  | 150 |  | C | Hysteresis = 20C | 3 |
| Minimum Off Time | TOFF |  | 100 |  | ns |  | 3 |
| Minimum On Time | TON |  | 100 |  | ns |  | 3 |
| EN Threshold Hysteresis |  |  | 320 |  | mV |  | 3 |
| Supply Voltage | VIN | -0.3 |  | 60 | V |  | 2 |
| BST to SW |  | -0.3 |  | 5 | V |  | 2 |
| All Other Pins |  | -0.3 |  | 5 | V |  | 2 |
| Continuous Power Dissipation SOIC8E |  |  |  | 2.5 | W | TA = +25°C | 2 |
| Junction Temperature | TJ |  |  | 150 | °C |  | 2 |
| Storage Temperature |  | -65 |  | 150 | °C |  | 2 |
| Supply Voltage VIN | VIN | 3.8 |  | 55 | V |  | 2 |
| Output Voltage VOUT | VOUT | 0.8 |  | 52 | V |  | 2 |
| Operating Junction Temperature | TJ | -40 |  | 125 | °C |  | 2 |
| Thermal Resistance Junction-Ambient SOIC8 (Exposed Pad) | θJA |  | 50 |  | °C/W | Measured on JESD51-7 4-layer board | 2 |
| Thermal Resistance Junction-Case SOIC8 (Exposed Pad) | θJC |  | 10 |  | °C/W | Measured on JESD51-7 4-layer board | 2 |

## CAD (KiCad official)

- Symbol: `MPQ4559DN-LF-Z`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `mpq4559dn-lf-z-etched.step` / `mpq4559dn-lf-z-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mpq4559dn-lf-z.step` / `mpq4559dn-lf-z.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Monolithic Power Systems datasheet](docs/mpq4559dn-lf-z-datasheet.pdf) (19 pp, sha256 `022a6df274a2c6c7`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mpq4559dn-lf-z-datasheet.pdf)