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Contents

README

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MPQ4314GRE-AEC1-Z

MONOLITHIC POWER SYSTEMS INC. · Global Sourcing Parts · QFN-20(4x4)

MPQ4314GRE-AEC1-Z from MONOLITHIC POWER SYSTEMS INC., in a QFN-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MODE input AAM or FCCM select: pull high for forced continuous conduction mode (FCCM), pull low for advanced asynchronous modulation (AAM) under light loads; do not float this pin.
2 SYNCIN input SYNC input accepting a 350kHz to 1000kHz clock to synchronize the internal oscillator; do not float, and a ≤51kΩ resistor to GND is recommended if the external clock's pull-down capability is insufficient.
3 VIN power_in Input supply for the internal control circuitry and the power MOSFET connected to SW; place a decoupling capacitor from VIN to ground as close to the pin as possible.
4 PGND power_in Power ground for the power stage.
5 PGND power_in Power ground for the power stage.
6 BST passive Positive supply for the high-side MOSFET driver; connect a bypass capacitor between BST and SW.
7 SW output Switch node, the output of the internal power MOSFET.
8 SW output Switch node, the output of the internal power MOSFET.
9 EN input Enable input: pulling below the 0.85V threshold shuts down the chip and pulling above the 1V threshold enables it.
10 PGND power_in Power ground for the power stage.
11 PGND power_in Power ground for the power stage.
12 VIN power_in Input supply for the internal control circuitry and the power MOSFET connected to SW; place a decoupling capacitor from VIN to ground as close to the pin as possible.
13 SYNCO output SYNC output providing a clock 180° out of phase with the internal oscillator (opposite the SYNCIN clock); float if not used.
14 PG output Open-drain power good output that requires a pull-up to the power source when used; goes high when VOUT is within 95% to 105% of nominal and low when VOUT is above 106.5% or below 93.5%.
15 NC unconnected Not connected; float this pin.
16 VCC power_out Bias supply for the internal control circuit and gate drivers; a decoupling capacitor to ground must be placed close to this pin.
17 AGND power_in Analog ground for the control circuitry.
18 FB input Feedback input; connect to the center point of the external resistor divider between VOUT and AGND, with a feedback threshold voltage (VFB) of 0.815V, and keep the divider close to FB with no vias on the FB traces.
19 SS passive Soft-start input; a capacitor from SS to GND sets the soft-start time, and the device sources 13μA from SS at start-up.
20 FREQ passive Switching frequency configuration; a resistor from this pin to ground sets fSW per the fSW vs. RFREQ curve on page 15.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer MONOLITHIC POWER SYSTEMS INC.
Package QFN-20(4x4)
Category Global Sourcing Parts
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN UVLO rising threshold VIN_UVLO_RISING 2.8 3 3.2 V 6
VIN UVLO falling threshold VIN_UVLO_FALLING 2.5 2.7 2.9 V 6
VCC voltage VCC 4.6 4.9 5.2 V IVCC = 0A 6
VCC regulation VCC 1 4 % IVCC = 30mA 6
VIN quiescent current (sleep mode) IQ 18 26 μA FB = 0.85V, no load, (sleep mode) 6
VIN shutdown current ISHDN 1.7 3.5 μA EN = 0V 6
FB reference voltage VFB 0.807 0.815 0.823 V VIN = 3.3V to 45V, TJ = 25C 6
FB reference voltage VFB 0.799 0.815 0.831 V VIN = 3.3V to 45V 6
FB current (adjustable-output version) IFB -50 0 50 nA VFB = 0.85V, adjustable-output version 6
Switching frequency fSW 420 470 520 kHz RFREQ = 62kΩ 6
Switching frequency fSW 820 1000 1180 kHz RFREQ = 26.1kΩ 6
SYNCIN clock range fSYNC 350 1000 kHz External clock 6
SYNCO high voltage VSYNCO_HIGH 3.3 4.5 V ISYNCO = -1mA 6
HS current limit ILIMIT 6.4 8 9.6 A Duty cycle = 30% 6
LS valley current limit ILIMIT_VALLEY 4.8 6 7.2 A 6
Zero-current detection (ZCD) current IZCD -0.15 0.1 0.35 A AAM mode 7
Low-side (LS) reverse current limit ILIMIT_REVERSE 2 4.5 7 A FCCM 7
Switch leakage current ISW_LKG 0.01 1 µA 7
High-side MOSFET on resistance RON_HS 48 80 mΩ VBST - VSW = 5V 7
Low-side MOSFET on resistance RON_LS 20 40 mΩ VCC = 5V 7
Soft-start current ISS 8 13 19 µA VSS = 0V 7
EN rising threshold VEN_RISING 0.8 1 1.2 V 7
EN falling threshold VEN_FALLING 0.65 0.85 1.05 V 7
PG rising threshold (VFB / VREF) PGRISING 92 95 98 % VFB rising 7
PG rising threshold (VFB / VREF) PGRISING 102 105 108 % VFB falling 7
PG falling threshold (VFB / VREF) PGFALLING 90.5 93.5 96.5 % VFB falling 7
PG falling threshold (VFB / VREF) PGFALLING 103.5 106.5 109.5 % VFB rising 7
PG output voltage low VPG_LOW 0.1 0.3 V ISINK = 1mA 7
Input supply voltage (VIN, EN) absolute maximum -0.3 50 V 5
Switch node voltage (SW) absolute maximum -0.3 V 5
All other pins absolute maximum -0.3 5.5 V 5
Operating junction temperature TJ 150 °C 5
Storage temperature -65 150 °C 5
ESD human body model (HBM) -2 2 kV 5
ESD charged device model (CDM) -750 750 V 5
Supply voltage (VIN) VIN 3.3 45 V 5
Output voltage (VOUT) VOUT 0.815 V 5
Operating junction temperature (TJ) TJ -40 150 °C 5
VIN UVLO hysteresis VIN_UVLO_HYS 280 mV 6
VCC current limit ILIMIT_VCC 100 mA VCC = 4V 6
VIN quiescent current (switching, AAM) IQ_ACTIVE 20 μA MODE = GND (AAM mode), switching, no load, RFB_UP = 1MΩ, RFB_DOWN = 316kΩ 6
VIN quiescent current (switching, FCCM) IQ_ACTIVE 40 mA MODE = high (FCCM), switching, fSW = 2MHz, no load 6
VIN quiescent current (switching, FCCM) IQ_ACTIVE 9.5 mA MODE = high (FCCM), switching, fSW = 470kHz, no load 6
Minimum on time tON_MIN 100 ns 6
Minimum off time tOFF_MIN 80 ns 6
SYNCIN voltage rising threshold VSYNC_RISING 1.8 V 6
SYNCIN voltage falling threshold VSYNC_FALLING 0.4 V 6
SYNCO low voltage VSYNCO_LOW 0.4 V ISYNCO = 1mA 6
PG rising delay tPG_R_DELAY 35 µs 7
PG falling delay tPG_F_DELAY 35 µs 7
Thermal shutdown TSD 170 °C 7
Thermal shutdown hysteresis TSD_HYS 20 °C 7
EN hysteresis voltage VEN_HYS 190 mV 7
MODE rising threshold VMODE_RISING 1.8 V 7
MODE falling threshold VMODE_FALLING 0.4 V 7
Thermal resistance junction-to-case (QFN-20) θJC 9 °C/W JESD51-7, 4-layer PCB (note 4) 5

CAD (KiCad official)

  • Symbol: MPQ4314GRE-AEC1-Z
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20(4x4) (KiCad packages3D, STEP)
  • 3D model files: mpq4314gre-aec1-z-etched.step / mpq4314gre-aec1-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mpq4314gre-aec1-z.step / mpq4314gre-aec1-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MONOLITHIC POWER SYSTEMS INC. datasheet (39 pp, sha256 8c62892d92511281, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF