component
MPQ1530DQ-AEC1-LF-Z
Public Made by Adomby adom
Monolithic Power Systems DC-DC Converters, QFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MPQ1530DQ-AEC1-LF-Z
Monolithic Power Systems · DC-DC Converters · QFN-16(3x3)
MPQ1530DQ-AEC1-LF-Z from Monolithic Power Systems, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Step-up converter power switch node, the drain of the internal 250mΩ N-channel MOSFET, with an inductor connected from the input source to SW and a rectifier from SW to the main output. |
| 2 | CT | passive | Timing capacitor for power-supply soft-start and power-on sequencing, where a capacitor from CT to GND sets the soft-start and turn-on delay periods (10nF gives a 6ms soft-start period). |
| 3 | RDY | output | Regulators-not-ready flag that is high during startup and pulled low once all FB voltages exceed 80% of their thresholds, and a fault persisting for more than approximately 6ms (CT = 10nF) shuts down the entire chip. |
| 4 | FB1 | input | Step-up converter feedback input and inverting input of the internal error amplifier, with a resistive divider from the step-up output setting the output voltage. |
| 5 | COMP | passive | Step-up converter compensation node, the output of the error amplifier, which requires a series RC network to compensate the control loop. |
| 6 | IN | power_in | Internal power input supplying the MPQ1530, which must be bypassed to PGND with a 10μF or greater capacitor; operating input range is 2.7V to 5.5V. |
| 7 | GND | power_in | Signal ground for the control circuitry, to be connected to PGND at one point as close to the IC as possible. |
| 8 | REF | power_out | 1.25V reference voltage output, which must be bypassed to GND with a 0.1μF or greater capacitor and connects to the low-side resistor of the negative linear regulator feedback string. |
| 9 | FB2 | input | Negative linear regulator feedback input with a regulation threshold of GND, with the feedback resistor string connected between GL and REF. |
| 10 | FB3 | input | Positive linear regulator feedback input with a regulation threshold of 1.25V, with the feedback resistor string connected between GH and GND. |
| 11 | EN | input | On/off control input where driving EN high turns the MPQ1530 on and driving it low immediately disables all outputs; connect EN to IN for automatic startup. |
| 12 | GL | power_out | Negative linear regulator output that supplies up to 20mA to the load and must be bypassed to GND with a 1μF or greater, low-ESR ceramic capacitor. |
| 13 | IN2 | power_in | Negative linear regulator input driven by an inverting charge pump from SW, which can go as low as -20V; for the QFN package the exposed pad must be connected to this pin. |
| 14 | GH | power_out | Positive linear regulator output that supplies as much as 20mA to the load and must be bypassed to GND with a 1μF or greater, low-ESR ceramic capacitor. |
| 15 | IN3 | power_in | Positive linear regulator input driven by a doubling, tripling, or quadrupling charge pump from SW, which can go as high as 38V. |
| 16 | PGND | power_in | Power ground that is the source of the internal 250mΩ N-channel MOSFET switch and must be connected to GND as close to the MPQ1530 as possible. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | QFN-16(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (IN) absolute maximum | -0.3 | 6 | V | 2 | |||
| SW Voltage | -0.3 | 25 | V | 2 | |||
| IN2, GL Voltage | -25 | 0.3 | V | 2 | |||
| IN3, GH Voltage | -0.3 | 40 | V | 2 | |||
| IN2 to IN3 Voltage | -0.3 | 60 | V | 2 | |||
| All Other Pins | -0.3 | 6 | V | 2 | |||
| Junction Temperature | 125 | °C | 2 | ||||
| Storage Temperature | -65 | 150 | °C | 2 | |||
| Input Voltage | 2.7 | 5.5 | V | 2 | |||
| Main Output Voltage | 22 | V | VIN to 22V as printed; lower limit given only as VIN | 2 | |||
| IN2, GL Voltage | -20 | 0 | V | 2 | |||
| IN3, GH Voltage | 0 | 38 | V | 2 | |||
| Operating Junction Temp. (TJ) | TJ | -40 | 125 | °C | 2 | ||
| Input Voltage Range | VIN | 2.7 | 5.5 | V | 3 | ||
| IN Undervoltage Lockout Threshold | VUVLO | 2.25 | 2.65 | V | IN Rising | 3 | |
| IN Shutdown Current | 0.5 | 1 | μA | VEN 0.3V | 3 | ||
| IN Quiescent Current | 1.3 | 1.6 | mA | VEN > 2V, VFB1 = 1.4V | 3 | ||
| EN Input High Voltage | VEN HIGH | 1.6 | V | EN Rising | 3 | ||
| EN Input Low Voltage | 0.3 | V | 3 | ||||
| Switching Frequency | fSW | 1 | 1.4 | MHz | 3 | ||
| Maximum Duty Cycle | DM | 85 | 90 | % | 3 | ||
| COMP Maximum Output Current | -100 | 100 | μA | 3 | |||
| FB1, FB3 Regulation Voltage | 1.22 | 1.25 | 1.28 | V | 3 | ||
| FB2 Regulation Voltage | -25 | 0 | 25 | mV | 3 | ||
| FB1, FB3 Input Bias Current | -100 | 100 | nA | VFB1 = VFB3 = 1.25V | 3 | ||
| FB2 Input Bias Current | -100 | 100 | nA | VFB2 = 0V | 3 | ||
| REF Regulation Voltage | 1.22 | 1.25 | 1.28 | V | IREF = 50μA | 3 | |
| REF Load Regulation | 1 | 1.2 | % | 0μA < IREF < 200μA | 3 | ||
| SW Current Limit | ILIM | 2.5 | 3.6 | A | TJ=+25°C | 3 | |
| SW Current Limit | ILIM | 2.2 | 3.6 | A | TJ=-40°C to +125°C | 3 | |
| SW Leakage Current | 0.5 | 1 | μA | VSW = 22V | 3 | ||
| GL Dropout Voltage | 0.1 | 0.3 | V | VGL = -10V, IGL = -20mA | 3 | ||
| GH Dropout Voltage | 0.45 | 1 | V | VGH = 20V, IGH = 20mA | 3 | ||
| GL Leakage Current | 1 | μA | VIN2 = -15V, VGL = GND | 3 | |||
| GH Leakage Current | 1 | μA | VIN3 = 25V, VGH = GND | 3 | |||
| IN Undervoltage Lockout Hysteresis | 100 | mV | 3 | ||||
| EN Hysteresis | 250 | mV | 3 | ||||
| EN Input Bias Current | 1 | μA | 3 | ||||
| Soft Start Period | 6 | ms | CCT = 10nF | 3 | |||
| Regulator #2 Turn-On/Turn-Off Delay | 3 | μs | 3 | ||||
| Error Amplifier Voltage Gain | AvEA | 400 | V/V | 3 | |||
| Error Amplifier Transconductance | GmEA | 1000 | μA/V | 3 | |||
| SW On Resistance | 250 | mΩ | VIN = 5V | 3 | |||
| SW On Resistance | 400 | mΩ | VIN = 3V | 3 | |||
| Thermal Shutdown | 160 | °C | 3 | ||||
| Thermal Resistance Junction-to-Ambient QFN16 (3 x 3mm) | θJA | 60 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
MPQ1530DQ-AEC1-LF-Z - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
mpq1530dq-aec1-lf-z-etched.step/mpq1530dq-aec1-lf-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mpq1530dq-aec1-lf-z.step/mpq1530dq-aec1-lf-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems datasheet (15 pp, sha256
73dd9dbff8c2959c, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MPQ1530DQ-AEC1-LF-Z
**Monolithic Power Systems** · DC-DC Converters · QFN-16(3x3)
MPQ1530DQ-AEC1-LF-Z from Monolithic Power Systems, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Step-up converter power switch node, the drain of the internal 250mΩ N-channel MOSFET, with an inductor connected from the input source to SW and a rectifier from SW to the main output. |
| 2 | CT | passive | Timing capacitor for power-supply soft-start and power-on sequencing, where a capacitor from CT to GND sets the soft-start and turn-on delay periods (10nF gives a 6ms soft-start period). |
| 3 | RDY | output | Regulators-not-ready flag that is high during startup and pulled low once all FB voltages exceed 80% of their thresholds, and a fault persisting for more than approximately 6ms (CT = 10nF) shuts down the entire chip. |
| 4 | FB1 | input | Step-up converter feedback input and inverting input of the internal error amplifier, with a resistive divider from the step-up output setting the output voltage. |
| 5 | COMP | passive | Step-up converter compensation node, the output of the error amplifier, which requires a series RC network to compensate the control loop. |
| 6 | IN | power_in | Internal power input supplying the MPQ1530, which must be bypassed to PGND with a 10μF or greater capacitor; operating input range is 2.7V to 5.5V. |
| 7 | GND | power_in | Signal ground for the control circuitry, to be connected to PGND at one point as close to the IC as possible. |
| 8 | REF | power_out | 1.25V reference voltage output, which must be bypassed to GND with a 0.1μF or greater capacitor and connects to the low-side resistor of the negative linear regulator feedback string. |
| 9 | FB2 | input | Negative linear regulator feedback input with a regulation threshold of GND, with the feedback resistor string connected between GL and REF. |
| 10 | FB3 | input | Positive linear regulator feedback input with a regulation threshold of 1.25V, with the feedback resistor string connected between GH and GND. |
| 11 | EN | input | On/off control input where driving EN high turns the MPQ1530 on and driving it low immediately disables all outputs; connect EN to IN for automatic startup. |
| 12 | GL | power_out | Negative linear regulator output that supplies up to 20mA to the load and must be bypassed to GND with a 1μF or greater, low-ESR ceramic capacitor. |
| 13 | IN2 | power_in | Negative linear regulator input driven by an inverting charge pump from SW, which can go as low as -20V; for the QFN package the exposed pad must be connected to this pin. |
| 14 | GH | power_out | Positive linear regulator output that supplies as much as 20mA to the load and must be bypassed to GND with a 1μF or greater, low-ESR ceramic capacitor. |
| 15 | IN3 | power_in | Positive linear regulator input driven by a doubling, tripling, or quadrupling charge pump from SW, which can go as high as 38V. |
| 16 | PGND | power_in | Power ground that is the source of the internal 250mΩ N-channel MOSFET switch and must be connected to GND as close to the MPQ1530 as possible. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | QFN-16(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (IN) absolute maximum | | -0.3 | | 6 | V | | 2 |
| SW Voltage | | -0.3 | | 25 | V | | 2 |
| IN2, GL Voltage | | -25 | | 0.3 | V | | 2 |
| IN3, GH Voltage | | -0.3 | | 40 | V | | 2 |
| IN2 to IN3 Voltage | | -0.3 | | 60 | V | | 2 |
| All Other Pins | | -0.3 | | 6 | V | | 2 |
| Junction Temperature | | | | 125 | °C | | 2 |
| Storage Temperature | | -65 | | 150 | °C | | 2 |
| Input Voltage | | 2.7 | | 5.5 | V | | 2 |
| Main Output Voltage | | | | 22 | V | VIN to 22V as printed; lower limit given only as VIN | 2 |
| IN2, GL Voltage | | -20 | | 0 | V | | 2 |
| IN3, GH Voltage | | 0 | | 38 | V | | 2 |
| Operating Junction Temp. (TJ) | TJ | -40 | | 125 | °C | | 2 |
| Input Voltage Range | VIN | 2.7 | | 5.5 | V | | 3 |
| IN Undervoltage Lockout Threshold | VUVLO | 2.25 | | 2.65 | V | IN Rising | 3 |
| IN Shutdown Current | | | 0.5 | 1 | μA | VEN 0.3V | 3 |
| IN Quiescent Current | | | 1.3 | 1.6 | mA | VEN > 2V, VFB1 = 1.4V | 3 |
| EN Input High Voltage | VEN HIGH | 1.6 | | | V | EN Rising | 3 |
| EN Input Low Voltage | | | | 0.3 | V | | 3 |
| Switching Frequency | fSW | 1 | 1.4 | | MHz | | 3 |
| Maximum Duty Cycle | DM | 85 | 90 | | % | | 3 |
| COMP Maximum Output Current | | -100 | | 100 | μA | | 3 |
| FB1, FB3 Regulation Voltage | | 1.22 | 1.25 | 1.28 | V | | 3 |
| FB2 Regulation Voltage | | -25 | 0 | 25 | mV | | 3 |
| FB1, FB3 Input Bias Current | | -100 | | 100 | nA | VFB1 = VFB3 = 1.25V | 3 |
| FB2 Input Bias Current | | -100 | | 100 | nA | VFB2 = 0V | 3 |
| REF Regulation Voltage | | 1.22 | 1.25 | 1.28 | V | IREF = 50μA | 3 |
| REF Load Regulation | | | 1 | 1.2 | % | 0μA < IREF < 200μA | 3 |
| SW Current Limit | ILIM | 2.5 | | 3.6 | A | TJ=+25°C | 3 |
| SW Current Limit | ILIM | 2.2 | | 3.6 | A | TJ=-40°C to +125°C | 3 |
| SW Leakage Current | | | 0.5 | 1 | μA | VSW = 22V | 3 |
| GL Dropout Voltage | | | 0.1 | 0.3 | V | VGL = -10V, IGL = -20mA | 3 |
| GH Dropout Voltage | | | 0.45 | 1 | V | VGH = 20V, IGH = 20mA | 3 |
| GL Leakage Current | | | | 1 | μA | VIN2 = -15V, VGL = GND | 3 |
| GH Leakage Current | | | | 1 | μA | VIN3 = 25V, VGH = GND | 3 |
| IN Undervoltage Lockout Hysteresis | | | 100 | | mV | | 3 |
| EN Hysteresis | | | 250 | | mV | | 3 |
| EN Input Bias Current | | | 1 | | μA | | 3 |
| Soft Start Period | | | 6 | | ms | CCT = 10nF | 3 |
| Regulator #2 Turn-On/Turn-Off Delay | | | 3 | | μs | | 3 |
| Error Amplifier Voltage Gain | AvEA | | 400 | | V/V | | 3 |
| Error Amplifier Transconductance | GmEA | | 1000 | | μA/V | | 3 |
| SW On Resistance | | | 250 | | mΩ | VIN = 5V | 3 |
| SW On Resistance | | | 400 | | mΩ | VIN = 3V | 3 |
| Thermal Shutdown | | | 160 | | °C | | 3 |
| Thermal Resistance Junction-to-Ambient QFN16 (3 x 3mm) | θJA | | 60 | | °C/W | | 2 |
## CAD (KiCad official)
- Symbol: `MPQ1530DQ-AEC1-LF-Z`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: QFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `mpq1530dq-aec1-lf-z-etched.step` / `mpq1530dq-aec1-lf-z-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mpq1530dq-aec1-lf-z.step` / `mpq1530dq-aec1-lf-z.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Monolithic Power Systems datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8601147858899873792) (15 pp, sha256 `73dd9dbff8c2959c`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mpq1530dq-aec1-lf-z-datasheet.pdf)