component
MP8774HGQ-Z
Public Made by Adomby adom
Monolithic Power Systems DC-DC Converters, QFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 13d ago |
| viewers | 13d ago |
| mp8774hgq-z-etched.glb | 13d ago |
| mp8774hgq-z-etched.step | 13d ago |
| mp8774hgq-z-hero.glb | 13d ago |
| mp8774hgq-z-hero.overlay.json | 13d ago |
| mp8774hgq-z.glb | 13d ago |
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| mp8774hgq-z.lbr | 13d ago |
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MP8774HGQ-Z
Monolithic Power Systems · DC-DC Converters · QFN-16(3x3)
MP8774HGQ-Z from Monolithic Power Systems, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connection; NC must be left floating. |
| 2 | BST | power_out | Bootstrap; a capacitor between SW and BST forms the floating high-side driver supply, and a BST resistor below 4.7Ω is recommended. |
| 3 | EN | input | Enable; pull EN high to enable the device (rising threshold 1.25V typical, falling threshold 1V typical), and when floating it is pulled down to GND by an internal 3.3MΩ resistor. |
| 4 | FB | input | Feedback; sets the output voltage when connected to the tap of an external resistor divider between the output and GND. |
| 5 | AGND | power_in | Signal ground, not connected to system ground internally, so it must be tied to system ground in the PCB layout. |
| 6 | SS | passive | Soft start; a capacitor across SS and GND sets the soft-start time and avoids inrush current at start-up, and an SS capacitor below 4.7nF should be avoided. |
| 7 | PG | output | Power good open-drain output that changes state when UVP, OCP, OTP, or OV occurs. |
| 8 | VIN | power_in | Supply voltage input operating from a 3V to 18V rail, decoupled by capacitor C1 and connected with a wide PCB trace. |
| 9 | PGND | power_in | System ground and reference ground of the regulated output voltage, recommended to be connected to GND with copper and vias. |
| 10 | PGND | power_in | System ground and reference ground of the regulated output voltage, recommended to be connected to GND with copper and vias. |
| 11 | PGND | power_in | System ground and reference ground of the regulated output voltage, recommended to be connected to GND with copper and vias. |
| 12 | PGND | power_in | System ground and reference ground of the regulated output voltage, recommended to be connected to GND with copper and vias. |
| 13 | PGND | power_in | System ground and reference ground of the regulated output voltage, recommended to be connected to GND with copper and vias. |
| 14 | VCC | power_out | Internal 3.4V bias supply output that must be decoupled with a 1µF capacitor placed close to VCC and GND. |
| 15 | NC | unconnected | No connection; NC must be left floating. |
| 16 | SW | output | Switch output that must be connected with a wide PCB trace. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | QFN-16(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (VIN) absolute maximum | VIN | -0.3 | 20 | V | 3 | ||
| Switch output voltage VSW (DC) | VSW | -0.3 | V | upper limit printed as VIN + 0.7V | 3 | ||
| Switch output voltage VSW transient undershoot | VSW | -5 | V | < 10ns | 3 | ||
| Switch output voltage VSW transient overshoot | VSW | 23 | V | < 10ns | 3 | ||
| All other pins voltage | -0.3 | 4 | V | 3 | |||
| Continuous power dissipation | 3.2 | W | TA = 25°C | 3 | |||
| Junction temperature | 150 | °C | 3 | ||||
| Storage temperature | -65 | 125 | °C | 3 | |||
| Supply voltage (VIN) | VIN | 3 | 18 | V | 3 | ||
| Output voltage (VOUT) | VOUT | 0.6 | 12 | V | upper limit printed as VIN * DMAX or 12V max | 3 | |
| Operating junction temperature (TJ) | TJ | -40 | 125 | °C | 3 | ||
| Input voltage range | VIN | 3 | 18 | V | 4 | ||
| Supply current (shutdown) | IIN | 5 | µA | VEN = 0V | 4 | ||
| Supply current (quiescent) | IQ | 100 | 150 | µA | VEN = 2V, VFB = 0.65V | 4 | |
| Switch leakage | SWLKG | 1 | µA | VEN = 0V, VSW = 17V, TJ = 25°C | 4 | ||
| Valley current limit | ILIMIT_VY | 12 | 14 | A | 4 | ||
| Switching frequency | fSW | 1200 | 1400 | 1600 | kHz | 4 | |
| Feedback voltage (TJ = 25°C) | VFB | 594 | 600 | 606 | mV | TJ = 25°C | 4 |
| Feedback voltage (TJ = -40°C to +125°C) | VFB | 591 | 600 | 609 | mV | TJ = -40°C to +125°C | 4 |
| Feedback current | IFB | 10 | 50 | nA | VFB = 700mV | 4 | |
| Soft-start current | ISS_START | 4 | 6 | 8 | µA | 4 | |
| EN rising threshold | VEN RISING | 1.1 | 1.25 | 1.4 | V | 4 | |
| EN falling threshold | VEN FALLING | 0.9 | 1 | 1.1 | V | 4 | |
| VCC under-voltage lockout threshold rising | VCCVth | 2.6 | 2.8 | 3 | V | 4 | |
| Power good UV rising threshold | PGUVvth_Hi | 0.85 | 0.9 | 0.95 | VFB | 5 | |
| Power good UV falling threshold | PGUVvth_Lo | 0.75 | 0.8 | 0.85 | VFB | 5 | |
| Power good OV rising threshold | PGOVvth_Hi | 1.15 | 1.2 | 1.25 | VFB | 5 | |
| Power good OV falling threshold | PGOVvth_Lo | 1.05 | 1.1 | 1.15 | VFB | 5 | |
| Power good sink current capability | VPG Sink | 0.4 | V | Sink 4mA | 5 | ||
| Switch on resistance (HS) | HSRDS(ON) | 16 | mΩ | VBST-SW = 3.3V | 4 | ||
| Switch on resistance (LS) | LSRDS(ON) | 5.5 | mΩ | VCC = 3.3V | 4 | ||
| Short hiccup duty cycle | DHICCUP | 10 | % | 4 | |||
| ZCD current | IZCD | 200 | mA | 4 | |||
| Minimum on time | tON_MIN | 50 | ns | 4 | |||
| Minimum off time | tOFF_MIN | 100 | ns | 4 | |||
| EN pull-down resistor | REN_PD | 1.2 | MΩ | 4 | |||
| VCC under-voltage lockout hysteresis | VCCHYS | 350 | mV | 4 | |||
| VCC regulator output | VCC | 3.4 | V | 4 | |||
| VCC load regulation | RegVCC | 3 | % | ICC = 5mA | 4 | ||
| Power good delay | PGTd | 50 | µs | Both edges | 5 | ||
| Power good leakage current | IPG_LEAK | 10 | μA | VPG = 5V | 5 | ||
| Thermal shutdown | TSD | 150 | °C | 5 | |||
| Thermal hysteresis | TSD-HYS | 20 | °C | 5 | |||
| Thermal resistance junction-to-ambient (QFN-16, EV8774H-Q-00A 4-layer PCB) | θJA | 38 | °C/W | EV8774H-Q-00A, 4-layer PCB | 3 | ||
| Thermal resistance junction-to-case (QFN-16, EV8774H-Q-00A) | θJC | 10 | °C/W | EV8774H-Q-00A | 3 | ||
| Thermal resistance junction-to-ambient (QFN-16, JESD51-7) | θJA | 50 | °C/W | JESD51-7 JEDEC board, simulated | 3 | ||
| Thermal resistance junction-to-case (QFN-16, JESD51-7) | θJC | 12 | °C/W | JESD51-7 JEDEC board, simulated | 3 |
CAD (KiCad official)
- Symbol:
MP8774HGQ-Z - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
mp8774hgq-z-etched.step/mp8774hgq-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp8774hgq-z.step/mp8774hgq-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems datasheet (23 pp, sha256
008cd9554ecb7672, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).