component
MP7740DN-LF-Z
Public Made by Adomby adom
MONOLITHIC POWER SYSTEMS Global Sourcing Parts, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 11d ago |
| viewers | 11d ago |
| mp7740dn-lf-z-etched.glb | 11d ago |
| mp7740dn-lf-z-etched.step | 11d ago |
| mp7740dn-lf-z-hero.glb | 11d ago |
| mp7740dn-lf-z-hero.overlay.json | 11d ago |
| mp7740dn-lf-z.glb | 11d ago |
| mp7740dn-lf-z.kicad_mod | 11d ago |
| mp7740dn-lf-z.kicad_sym | 11d ago |
| mp7740dn-lf-z.lbr | 11d ago |
| mp7740dn-lf-z.step | 11d ago |
| package.json | 11d ago |
| page.json | 11d ago |
| README.md | 11d ago |
MP7740DN-LF-Z
MONOLITHIC POWER SYSTEMS · Global Sourcing Parts · SOIC-8-EP
MP7740DN-LF-Z from MONOLITHIC POWER SYSTEMS, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PIN | input | Amplifier positive input; use a resistive voltage divider to set the voltage at PIN to VDD/2, with common mode range 0 to VDD-1.5V. |
| 2 | NIN | input | Amplifier negative input; drive the input signal and close the feedback loop at NIN. |
| 3 | AGND | power_in | Analog ground; connect AGND to PGND at a single point. |
| 4 | EN | input | Enable input; drive high (2.5V or greater) to turn on the amplifier and low (below 1V) to turn it off, with absolute maximum of 6V. |
| 5 | BS | passive | High-side MOSFET bootstrap input; a capacitor from BS to SW supplies the gate drive current to the internal high-side MOSFET. |
| 6 | VDD | power_in | Power supply input for the output stage and internal control circuitry, operating 9.5V to 36V (40V absolute max), bypassed to PGND with a 1µF X7R capacitor close to pins 6 and 8. |
| 7 | SW | output | Switched power output; connect the LC filter between SW and the output coupling capacitor. |
| 8 | PGND | power_in | Power ground; connect PGND to AGND at a single point. |
| 9 | EP | passive | Exposed pad on the backside; connect to the GND plane for proper thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MONOLITHIC POWER SYSTEMS |
| Package | SOIC-8-EP |
| Category | Global Sourcing Parts |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Standby Current | 20 | 50 | µA | VEN = 0V | 3 | ||
| Quiescent Current | 1.5 | 3 | mA | SW=0V | 3 | ||
| PIN, NIN Input Common Mode Voltage Range | 0 | V | upper limit VDD, 1.5 (VDD/2 also printed) | 3 | |||
| PIN, NIN Input Current | 1 | 5 | µA | VPIN = VNIN = 12V | 3 | ||
| EN Enable Threshold Voltage Rising | VEN | 1.8 | 2.5 | V | VEN Rising | 3 | |
| EN Enable Threshold Voltage Falling | VEN | 0.8 | 1.2 | V | VEN Falling | 3 | |
| EN Enable Input Current | 1 | µA | VEN = 5V | 3 | |||
| SW On Resistance | 0.25 | Ω | Sourcing and Sinking | 3 | |||
| Short Circuit Current | 4.5 | A | Sourcing and Sinking | 3 | |||
| Thermal Shutdown Trip Point | 150 | °C | TJ Rising | 3 | |||
| Thermal Shutdown Hysteresis | 30 | °C | 3 | ||||
| Supply Voltage | VDD | 40 | V | 2 | |||
| BS Voltage | -0.3 | 6.5 | V | relative to VSW (VSW, 0.3V to VSW + 6.5V) | 2 | ||
| Enable Voltage | VEN | -0.3 | 6 | V | 2 | ||
| SW Voltage | VSW | -1 | V | -5V for <10ns; max VDD + 1V | 2 | ||
| PIN, NIN Voltage | VPIN, VNIN | -1 | V | max VDD + 1V | 2 | ||
| AGND to PGND | -0.3 | 0.3 | V | 2 | |||
| Continuous Power Dissipation | 2.5 | W | TA = +25°C | 2 | |||
| Junction Temperature | TJ | 150 | °C | 2 | |||
| Storage Temperature | -65 | 150 | °C | 2 | |||
| Operating Temperature | TA | -40 | 85 | °C | 2 | ||
| Thermal Resistance Junction-to-Ambient | θJA | 50 | °C | SOIC8E; JESD51-7, 4-layer PCB | 2 | ||
| Thermal Resistance Junction-to-Case | θJC | 8 | °C | SOIC8E; JESD51-7, 4-layer PCB | 2 | ||
| Standby Current (application circuit) | 130 | µA | Circuit of Figure 1, VEN = 0V | 3 | |||
| Quiescent Current (application circuit) | 13 | mA | Circuit of Figure 1 | 3 | |||
| Power Output 4Ω | POUT | 15 | W | f = 1KHz, THD+N = 10%, 4Ω Load | 3 | ||
| Power Output 8Ω | POUT | 8 | W | f = 1KHz, THD+N = 10%, 8Ω Load | 3 | ||
| THD+Noise 4Ω | 0.05 | % | POUT = 1W, f = 1kHz, 4Ω Load | 3 | |||
| THD+Noise 8Ω | 0.018 | % | POUT = 1W, f = 1kHz, 8Ω Load | 3 | |||
| Efficiency 4Ω | 90 | % | f = 1KHz, POUT = 15W, 4Ω Load | 3 | |||
| Efficiency 8Ω | 90 | % | f = 1KHz, POUT = 8W, 8Ω Load | 3 | |||
| Maximum Power Bandwidth | 20 | kHz | 3 | ||||
| Dynamic Range | 97 | dB | 3 | ||||
| Noise Floor | 103 | µV | A-Weighted | 3 |
CAD (KiCad official)
- Symbol:
MP7740DN-LF-Z - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
mp7740dn-lf-z-etched.step/mp7740dn-lf-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp7740dn-lf-z.step/mp7740dn-lf-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MONOLITHIC POWER SYSTEMS datasheet (12 pp, sha256
3e8a2ad7e634c2fb, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).