# MP6951GJ-Z

**Monolithic Power Systems** · AC-DC Controllers And Regulators · TSOT-23-6

MP6951GJ-Z from Monolithic Power Systems, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HVC | input | HV linear regulator input, with a recommended HVC-to-GND range of -1V to +150V and an absolute maximum range of -1V to +180V. |
| 2 | GND | power_in | Ground, serving as the reference for MOSFET source sensing. |
| 3 | TW | input | Sets the VDS ringing detection time window; it must be connected to GND through an external resistor, and the window is calculated from that resistor per Equation (1). |
| 4 | VDD | power_out | Linear regulator output that supplies power to the IC, with a recommended VDD-to-GND range of 4.5V to 13V and an absolute maximum of -0.3V to +14V. |
| 5 | DRV | output | MOSFET gate driver output, rated at -0.3V to +14V to GND under absolute maximum ratings. |
| 6 | SRD | input | MOSFET drain voltage sense, with a recommended SRD-to-GND range of -1V to +150V and an absolute maximum range of -1V to +180V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | TSOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD under-voltage lockout (UVLO) rising threshold | VUVLO | 4 | 4.2 | 4.4 | V |  | 5 |
| VDD UVLO hysteresis | VUVLO_HYS | 0.1 | 0.2 | 0.3 | V |  | 5 |
| VDD regulation voltage (HVC supplied) | VDD_HVC | 6.1 | 6.5 | 6.9 | V | SRD = 12V, HVC = 12V | 5 |
| VDD regulation voltage (SRD supplied) | VDD_SRD | 4.55 | 4.9 | 5.25 | V | SRD = 12V, HVC = 3V | 5 |
| VDD charge current (SRD) | IVDD_SRD | 23 | 43 | 63 | mA | VDD = 4V, SRD = 30V, CDD = 1µF | 5 |
| VDD charge current (HVC) | IVDD_HVC | 20 | 50 | 80 | mA | VDD = VDD_HVC - 1V, HVC = 12V, CDD = 1µF | 5 |
| VDD charge current (HVC) | IVDD_HVC | 40 | 72 | 105 | mA | VDD = VDD_HVC-1V, HVC = 30V, CDD = 1µF | 5 |
| Operating current | ICC |  | 2.3 | 3 | mA | VDD = 6.7V, CLOAD = 2.2nF, fSW = 100kHz | 5 |
| Operating current | ICC |  | 1.8 | 2.4 | mA | VDD = 5V, CLOAD=2.2nF, fSW = 100kHz | 5 |
| Forward regulation voltage (GND-SRD) | VFWD |  | 40 |  | mV |  | 5 |
| Turn on threshold (SRD-GND) | VON | -110 | -80 | -50 | mV |  | 5 |
| Turn off threshold (SRD-GND) | VOFF | -14 | -4 | 5 | mV |  | 5 |
| Turn-off blanking threshold (SRD-GND) | VB-OFF | 1.3 | 1.8 | 2.1 | V |  | 5 |
| Slew rate detection time window threshold | tW_SRD | 320 | 440 | 560 | ns | RTW = 100kΩ | 5 |
| VDRV (low) | VDRV-L |  | 5 | 15 | mV | ILOAD = 10mA | 6 |
| Maximum source current at high gate charge mode | ICH_HGC |  |  | 0.5 | A |  | 6 |
| Maximum source current at low gate charge mode | ICH_LGC |  |  | 100 | mA |  | 6 |
| Maximum sink current |  |  |  | 3 | A |  | 6 |
| Pull-down impedance |  |  | 0.5 | 1 | Ω | ILOAD = 10mA | 6 |
| HVC, SRD to GND voltage |  | -1 |  | 180 | V |  | 4 |
| VDD, DRV to GND voltage |  | -0.3 |  | 14 | V |  | 4 |
| Other pins to GND voltage |  | -0.3 |  | 6.5 | V |  | 4 |
| Continuous power dissipation | PD |  |  | 0.56 | W | TA = 25°C | 4 |
| Junction temperature | TJ |  |  | 150 | °C |  | 4 |
| Storage temperature |  | -55 |  | 150 | °C |  | 4 |
| HVC, SRD to GND |  | -1 |  | 150 | V |  | 4 |
| Maximum junction temperature | TJ |  |  | 125 | °C |  | 4 |
| Quiescent current | IQ |  | 355 |  | µA | VDD = 5V | 5 |
| Shutdown current | ISD(VDD) |  | 100 |  | µA | VDD = VUVLO - 0.1V | 5 |
| Input bias current on the SRD pin |  |  | 65 |  | µA | VDD = 100V | 5 |
| Input bias current on the SRD pin |  |  | 28 |  | µA | VDD = 30V | 5 |
| Turn-on delay | tDON_FAST |  | 30 |  | ns | CLOAD = 2.2nF | 5 |
| Turn-off delay | tDOFF |  | 20 |  | ns | CLOAD = 2.2nF | 5 |
| Turn-on delay during low gate charge mode | tDON_LGC |  | 300 |  | ns | CLOAD = 2.2nF | 5 |
| Turn-off propagation delay |  |  | 10 |  | ns |  | 5 |
| Turn-on blanking time | tMOT |  | 0.62 |  | us |  | 5 |
| Junction-to-case thermal resistance | θJC |  | 110 |  | °C/W | TSOT23-6, measured on JESD51-7, 4-layer PCB | 4 |

## CAD (KiCad official)

- Symbol: `MP6951GJ-Z`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-6`
- 3D model: TSOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `mp6951gj-z-etched.step` / `mp6951gj-z-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mp6951gj-z.step` / `mp6951gj-z.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Monolithic Power Systems datasheet](docs/mp6951gj-z-datasheet.pdf) (19 pp, sha256 `d7f5ec6ac29f1041`, retrieved 2026-11-05, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mp6951gj-z-datasheet.pdf)