component
MP6925AGS-Z
Public Made by Adomby adom
MONOLITHIC POWER SYSTEMS Global Sourcing Parts, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMP6925AGS-Z
MONOLITHIC POWER SYSTEMS · Global Sourcing Parts · SOIC-8
MP6925AGS-Z from MONOLITHIC POWER SYSTEMS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VG2 | output | MOSFET 2 gate driver output, with VG to VSS rated from -0.3V to +20V. |
| 2 | PGND | power_in | Power ground, which is the power switch return, with PGND to VSS rated from -0.3V to +0.3V. |
| 3 | LL | input | Light-load timing setting: connect a resistor to set light-load timing, leave floating to disable light-load mode (or connect a capacitor if light-load is disabled), and pull low to disable the gate driver, with LL to VSS rated from -0.3V to +6.5V. |
| 4 | VD2 | input | MOSFET 2 voltage-sense drain, with VD to VSS rated from -1V to +180V. |
| 5 | VSS | power_in | Source pin used as the reference for VD1 and VD2. |
| 6 | VD1 | input | MOSFET 1 voltage-sense drain, with VD to VSS rated from -1V to +180V. |
| 7 | VDD | power_in | Supply voltage, with VDD to VSS recommended operating range of 4.2V to 35V and absolute maximum of +38V. |
| 8 | VG1 | output | MOSFET 1 gate driver output, with VG to VSS rated from -0.3V to +20V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MONOLITHIC POWER SYSTEMS |
| Package | SOIC-8 |
| Category | Global Sourcing Parts |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD voltage range | 4.2 | 35 | V | 4 | |||
| VDD UVLO rising | 3.7 | 3.95 | 4.2 | V | 4 | ||
| VDD UVLO hysteresis | 0.13 | 0.185 | 0.24 | V | 4 | ||
| Operating current | ICC | 16 | 20 | mA | CLOAD = 4.7nF, fSW = 100kHz | 4 | |
| Quiescent current | IQ | 4.6 | 6 | mA | VSS - VD = 0.5V | 4 | |
| Shutdown current | 135 | 190 | µA | VDD = 4V, LL = 0V | 4 | ||
| Shutdown current | 155 | 210 | µA | VDD = 20V, LL = 0V | 4 | ||
| Light-load mode current | 175 | 225 | µA | 4 | |||
| Thermal shutdown | 150 | °C | 4 | ||||
| Thermal shutdown hysteresis | 10 | °C | 4 | ||||
| VSS - VD forward voltage | VFWD | 28 | 45 | 58 | mV | 4 | |
| Turn off threshold (VSS - VD) | VDRV-OFF | -56 | -40 | -20 | mV | 4 | |
| Turn-on delay | tDON | 80 | 140 | ns | CLOAD = 4.7nF, VGS = 2V | 4 | |
| Turn-on delay | tDON | 90 | 180 | ns | CLOAD = 10nF, VGS = 2V | 4 | |
| Input bias current on VD | 1 | µA | VD = 180V | 4 | |||
| Turn-on blanking time | tB_ON | 0.75 | 1.1 | 1.65 | µs | CLOAD = 4.7nF | 4 |
| Turn-off blanking time | tB_OFF | 210 | ns | CLOAD = 4.7nF | 4 | ||
| Turn-off blanking VDS threshold | VB_OFF | 1 | 1.7 | 2.5 | V | 4 | |
| Light-load enter pulse width | tLL | 1.7 | 2.3 | 3 | µs | RLL = 100kΩ | 4 |
| Light-load turn-on pulse width hysteresis | tLL-H | 0.45 | µs | RLL = 100kΩ | 4 | ||
| Light-load enter delay | tLL-D | 0.5 | 1 | 1.52 | ms | 4 | |
| Light-load enter pulse-width threshold (VG1/2 - VSS) | VLL-GS | 0.6 | V | 4 | |||
| Gate disable threshold on LL | VLL_DIS | 0.1 | 0.2 | 0.3 | V | 4 | |
| Light-load exit switch-on threshold (VDS) | VLL_DS | -330 | -230 | -130 | mV | 4 | |
| VG (low) | VG_L | 0.1 | V | ILOAD = 1mA | 4 | ||
| VG (high) | VG_H | 11.5 | 13 | V | VDD > 10V | 4 | |
| Turn-off propagation delay | 15 | ns | VD = VSS | 4 | |||
| Turn-off total delay | tDOFF | 35 | 80 | ns | VD = VSS, CLOAD = 4.7nF, RGATE = 0Ω, VGS = 2V | 4 | |
| Turn-off total delay | tDOFF | 45 | 100 | ns | VD = VSS, CLOAD = 10nF, RGATE = 0Ω, VGS = 2V | 4 | |
| Pull-down impedance | 0.6 | 1.5 | Ω | 4 | |||
| VDD - VSS (supply voltage, recommended operating) | VDD - VSS | 4.2 | 35 | V | 3 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 3 | ||
| VDD to VSS | -0.3 | 38 | V | 3 | |||
| PGND to VSS | -0.3 | 0.3 | V | 3 | |||
| VG to VSS | -0.3 | 20 | V | 3 | |||
| VD to VSS | -1 | 180 | V | 3 | |||
| LL to VSS | -0.3 | 6.5 | V | 3 | |||
| Junction temperature | 150 | °C | 3 | ||||
| Storage temperature | -55 | 150 | °C | 3 | |||
| ESD Human-body model (HBM) | -800 | 800 | V | 3 | |||
| ESD Charged-device model (CDM) | -1750 | 1750 | V | 3 | |||
| Thermal resistance junction-to-ambient (SOIC-8) | θJA | 90 | °C/W | Measured on JESD51-7, 4-layer PCB | 3 | ||
| Thermal resistance junction-to-case (SOIC-8) | θJC | 45 | °C/W | Measured on JESD51-7, 4-layer PCB | 3 |
CAD (KiCad official)
- Symbol:
MP6925AGS-Z - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mp6925ags-z-etched.step/mp6925ags-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp6925ags-z.step/mp6925ags-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MONOLITHIC POWER SYSTEMS datasheet (15 pp, sha256
294418f53842b8d0, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).