component
MP6910AGS-Z
Public Made by Adomby adom
Monolithic Power Systems Power Management - Specialized, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MP6910AGS-Z
Monolithic Power Systems · Power Management - Specialized · SOIC-8
MP6910AGS-Z from Monolithic Power Systems, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VS | power_in | MOSFET source, also used as the reference for VDD (ground reference of the IC); pins 1 and 4 are both VS. |
| 2 | VDD | power_in | Supply voltage, recommended range 8.3V to 24V relative to VS (absolute maximum 25V). |
| 3 | SENSE | input | MOSFET drain voltage sensing; an external resistor of about 300Ω to 1kΩ between SENSE and the MOSFET drain is recommended, and the pin is rated -1V to +180V relative to VS. |
| 4 | VS | power_in | MOSFET source, also used as the reference for VDD (ground reference of the IC); pins 1 and 4 are both VS. |
| 5 | VD | passive | MOSFET drain, rated -1.5V to +100V relative to VS; pins 5 to 8 are all VD. |
| 6 | VD | passive | MOSFET drain, rated -1.5V to +100V relative to VS; pins 5 to 8 are all VD. |
| 7 | VD | passive | MOSFET drain, rated -1.5V to +100V relative to VS; pins 5 to 8 are all VD. |
| 8 | VD | passive | MOSFET drain, rated -1.5V to +100V relative to VS; pins 5 to 8 are all VD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD voltage range | 8.3 | 24 | V | 4 | |||
| VDD UVLO rising | 6.2 | 7.2 | 8.2 | V | VDD = 12V, TJ = -40 ~ 125°C | 4 | |
| VDD UVLO hysteresis | 0.8 | 1.1 | 1.4 | V | VDD = 12V, TJ = -40 ~ 125°C | 4 | |
| VSS - VD forward voltage | VFWD | 45 | 65 | 85 | mV | 4 | |
| Turn-off threshold (VSS - VD) | 20 | 30 | 40 | mV | 4 | ||
| Minimum on time | tMIN | 0.6 | 1 | 1.7 | μs | 4 | |
| Light-load enter delay | tLL-Delay | 70 | 120 | 170 | μs | 4 | |
| Light-load enter pulse width | tLL | 1.4 | 2.2 | 3.6 | μs | 4 | |
| Light-load mode exit pulse-width threshold (VDS) | VLL-DS | -315 | -190 | -70 | mV | 4 | |
| Operating current | ICC | 2.6 | 4 | mA | fSW = 100kHz | 4 | |
| Light-load mode current | 255 | 350 | μA | 4 | |||
| Drain source on resistance | RDS(ON) | 15 | 18.8 | mΩ | VDD = 12V, ID = 2A | 4 | |
| Source-drain diode forward voltage | VSD | 0.8 | 1.2 | V | IS = 20A, VGS = 0V | 4 | |
| Drain source breakdown voltage | V(BR)DSS | 100 | V | 4 | |||
| Single-pulse avalanche energy | EAS | 100 | mJ | VPS=50V, VGS = 10V, L = 1.0mH | 4 | ||
| Turn-on delay | tDon | 100 | ns | 4 | |||
| Turn-off delay | tDoff | 30 | ns | 4 | |||
| Light-load enter pulse-width hysteresis | tLL-H | 0.27 | μs | 4 | |||
| Input capacitance | Ciss | 1925 | pF | VDS =40V, VGS = 0V, f = 1MHz | 4 | ||
| Output capacitance | Coss | 307 | pF | VDS =40V, VGS = 0V, f = 1MHz | 4 | ||
| Reverse transfer capacitance | Crss | 20 | pF | VDS =40V, VGS = 0V, f = 1MHz | 4 | ||
| Reverse recovery time | trr | 79 | ns | IF = 10A, dl/dt = 100A/μs | 4 | ||
| Diode reverse charge | Qrr | 106 | nC | IF = 10A, dl/dt = 100A/μs | 4 | ||
| VDD to VS | VDD | -0.3 | 25 | V | 3 | ||
| VD to VS | VD | -1.5 | 100 | V | 3 | ||
| SENSE to VS | SENSE | -1 | 180 | V | 3 | ||
| Pulsed drain current | 50 | A | Pulse width=100μs, duty cycle limited by maximum junction temperature | 3 | |||
| Junction temperature | TJ | 150 | °C | 3 | |||
| Storage temperature | -55 | 150 | °C | 3 | |||
| ESD HBM, SENSE pin | -2000 | 1200 | V | Human-body model | 3 | ||
| ESD HBM, other pins | -2000 | 2000 | V | Human-body model | 3 | ||
| ESD CDM | -2000 | 2000 | V | Charged-device model | 3 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 3 | ||
| VDD to VS (recommended) | VDD | 8.3 | 24 | V | 3 | ||
| Thermal resistance junction-to-ambient | θJA | 67 | °C/W | SOIC-8, JESD51-7, 4-layer PCB | 3 | ||
| Thermal resistance junction-to-case | θJC | 30 | °C/W | SOIC-8, JESD51-7, 4-layer PCB | 3 |
CAD (KiCad official)
- Symbol:
MP6910AGS-Z - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mp6910ags-z-etched.step/mp6910ags-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp6910ags-z.step/mp6910ags-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems datasheet (14 pp, sha256
6d40eba102fd8ddc, retrieved 2026-10-31, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).