component
MP6906GJ-Z
Public Made by Adomby adom
Monolithic Power Systems AC-DC Controllers And Regulators, TSOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MP6906GJ-Z
Monolithic Power Systems · AC-DC Controllers And Regulators · TSOT-23-6
MP6906GJ-Z from Monolithic Power Systems, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VG | output | Gate drive output for the external MOSFET, with VG high of 10.5V to 13V when VDD is above 10.5V and VG low of 0.1V max at 1mA load. |
| 2 | VSS | power_in | Ground and reference for VD, with the VSS-VD forward voltage regulated at a typical 23mV (12mV to 34mV). |
| 3 | VDD | power_in | Supply voltage with a 4.2V to 35V operating range and 4.2V UVLO rising threshold. |
| 4 | VD | input | FET drain voltage sense that is referenced to VSS, and VD can go as high as 180V per the datasheet. |
| 5 | LL | input | Light-load timing setting; a resistor RLL sets the light-load timing, leaving LL open prevents light-load mode, and pulling LL low disables the gate driver. |
| 6 | PGND | power_in | Power ground that is the return for the driver switch. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | TSOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to VSS | -0.3 | 38 | V | 3 | |||
| PGND to VSS | -0.3 | 0.3 | V | 3 | |||
| VG to VSS | -0.3 | 20 | V | 3 | |||
| VD to VSS | -1 | 180 | V | 3 | |||
| SYNC, LL, EN to VSS | -0.3 | 6.5 | V | 3 | |||
| Continuous power dissipation TSOT23-6 | 0.57 | W | TA = +25°C | 3 | |||
| Junction temperature | 150 | C | 3 | ||||
| Lead temperature (solder) | 260 | C | 3 | ||||
| Storage temperature | -55 | 150 | C | 3 | |||
| VDD to VSS operating range | 4.2 | 35 | V | 3 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 3 | ||
| VDD voltage range | 4.2 | 35 | V | 4 | |||
| Operating current | ICC | 8 | 10 | mA | CLOAD = 5nF, FSW = 100kHz | 4 | |
| Quiescent current | Iq | 2 | 3 | mA | VSS - VD = 0.5V | 4 | |
| Light-load mode current | 150 | 220 | µA | 4 | |||
| Enable UVLO rising | VEN-R | 1.2 | 1.5 | 1.8 | V | 4 | |
| Enable UVLO hysteresis | 0.1 | 0.2 | V | 4 | |||
| Internal pull-up current on EN | 10 | 18 | µA | 4 | |||
| VSS-VD forward voltage | Vfwd | 12 | 23 | 34 | mV | 4 | |
| Turn-off threshold (VSS-VD) | -6 | 3 | 12 | mV | 4 | ||
| Turn-on delay TDon (CLOAD = 5nF) | TDon | 200 | 300 | ns | CLOAD = 5nF, VGS = 2V | 4 | |
| Turn-on delay TDon (CLOAD = 10nF) | TDon | 250 | 450 | ns | CLOAD = 10nF, VGS = 2V | 4 | |
| Turn-on blanking time | TB_ON | 1.2 | 1.9 | 2.7 | µs | CLOAD = 5nF | 4 |
| Turn-off blanking VDS threshold | VB_OFF | 1.4 | 2 | V | 4 | ||
| Turn-off threshold on SYNC | VSYN | 1.6 | 2 | 2.4 | V | 4 | |
| Internal pull-down current on SYNC | 10 | 15 | µA | VSYNC = 5V | 4 | ||
| Light-load-enter SYNC duration | TSYN | 75 | 95 | 115 | µs | 4 | |
| Light-load-enter pulse width | TLL | 2.2 | 3.6 | 4.9 | µs | RLL = 200k | 4 |
| Gate disable threshold on LL | VLL_DIS | 0.2 | 0.31 | V | 4 | ||
| Turn-on threshold (VDS) | VLL-DS | -400 | -275 | -150 | mV | VDD = 12V | 4 |
| VG (low) | VG-L | 0.05 | 0.1 | V | ILOAD = 1mA | 4 | |
| VG (high) for VDD > 10.5V | VG-H | 10.5 | 12 | 13 | V | VDD > 10.5V | 4 |
| SYNC turn-off propagation delay | 40 | 70 | ns | 4 | |||
| Turn-off propagation delay | 25 | 50 | ns | VD = VSS | 4 | ||
| Turn-off total delay TDoff (CLOAD = 5nF) | TDoff | 35 | 60 | ns | VD = VSS, CLOAD = 5nF, RGATE = 0, VGS = 2V | 4 | |
| Turn-off total delay TDoff (CLOAD = 10nF) | TDoff | 45 | 95 | ns | VD = VSS, CLOAD = 10nF, RGATE = 0, VGS = 2V | 4 | |
| VDD UVLO rising | 4.2 | V | 4 | ||||
| VDD UVLO hysteresis | 0.13 | V | 4 | ||||
| Input bias current on VD | 1 | µA | VD = 180V | 4 | |||
| Light-load-enter pulse width hysteresis | TLL-H | 0.6 | µs | RLL = 200k | 4 | ||
| Thermal shutdown | 150 | oC | 4 | ||||
| Thermal shutdown hysteresis | 30 | oC | 4 | ||||
| Thermal resistance junction-to-ambient TSOT23-6 | θJA | 220 | C/W | JESD51-7, 4-layer PCB | 3 | ||
| Thermal resistance junction-to-case TSOT23-6 | θJC | 110 | C/W | 3 |
CAD (KiCad official)
- Symbol:
MP6906GJ-Z - Footprint:
Package_TO_SOT_SMD:TSOT-23-6 - 3D model: TSOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
mp6906gj-z-etched.step/mp6906gj-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp6906gj-z.step/mp6906gj-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems datasheet (17 pp, sha256
e26b694ac58cf712, retrieved 2026-11-02, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).