component
MP6539GV-Z
Public Made by Adomby adom
Monolithic Power Systems Others, QFN-28(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MP6539GV-Z
Monolithic Power Systems · Others · QFN-28(4x5)
MP6539GV-Z from Monolithic Power Systems, in a QFN-28(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference for the device; the exposed pad on the backside is also connected to GND. |
| 2 | VIN | power_in | Input supply voltage with a recommended operating range of +8V to 100V. |
| 3 | CSO | output | Current sense output and OCP off-time adjust; requires at least 1nF from CSO to ground for stability. |
| 4 | LDO | power_out | Gate drive LDO output that connects directly to VREG for currents up to about 5mA, or drives the base of an external NPN for higher current. |
| 5 | VREG | power_in | Gate driver supply voltage with a recommended operating range of 8.5V to 14V. |
| 6 | BSTA | power_out | Bootstrap output for phase A, with a bootstrap capacitor connected between SHA and BSTA and an absolute maximum of 120V. |
| 7 | SHA | passive | High-side source connection for phase A, which is the bootstrap capacitor reference node. |
| 8 | GHA | output | High-side gate drive output for phase A, driving the HS-FET gate with a 0.8A source and 1A sink capability. |
| 9 | GLA | output | Low-side gate drive output for phase A, driving the LS-FET gate with a 0.8A source and 1A sink capability. |
| 10 | BSTB | power_out | Bootstrap output for phase B, with a bootstrap capacitor connected between SHB and BSTB and an absolute maximum of 120V. |
| 11 | SHB | passive | High-side source connection for phase B, which is the bootstrap capacitor reference node. |
| 12 | GHB | output | High-side gate drive output for phase B, driving the HS-FET gate with a 0.8A source and 1A sink capability. |
| 13 | GLB | output | Low-side gate drive output for phase B, driving the LS-FET gate with a 0.8A source and 1A sink capability. |
| 14 | BSTC | power_out | Bootstrap output for phase C, with a bootstrap capacitor connected between SHC and BSTC and an absolute maximum of 120V. |
| 15 | SHC | passive | High-side source connection for phase C, which is the bootstrap capacitor reference node. |
| 16 | GHC | output | High-side gate drive output for phase C, driving the HS-FET gate with a 0.8A source and 1A sink capability. |
| 17 | GLC | output | Low-side gate drive output for phase C, driving the LS-FET gate with a 0.8A source and 1A sink capability. |
| 18 | LSS | passive | Low-side source connection to the shared current sense resistor; absolute maximum rating is -0.3V to 4V. |
| 19 | LSC | input | Phase C low-side input pin that controls the LS-FET gate together with HSC per the input logic truth table. |
| 20 | LSB | input | Phase B low-side input pin that controls the LS-FET gate together with HSB per the input logic truth table. |
| 21 | LSA | input | Phase A low-side input pin that controls the LS-FET gate together with HSA per the input logic truth table. |
| 22 | HSC | input | Phase C high-side input pin that controls the HS-FET gate together with LSC per the input logic truth table. |
| 23 | HSB | input | Phase B high-side input pin that controls the HS-FET gate together with LSB per the input logic truth table. |
| 24 | HSA | input | Phase A high-side input pin that controls the HS-FET gate together with LSA per the input logic truth table. |
| 25 | nFAULT | output | Open-drain fault indication output that is driven logic low during a fault condition such as OCP or over-temperature. |
| 26 | nSLEEP | input | Sleep mode input where logic low enters low-power sleep and logic high enables the device, with an internal 450kΩ pulldown. |
| 27 | OCREF | input | Over-current protection reference input with a recommended voltage range of 0.125V to 2.4V. |
| 28 | DT | passive | Dead-time setting pin where a resistor to GND sets dead time per tDEAD = 0.044×R(kΩ) + 0.1 µs, and tying DT to GND applies the internal minimum. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | QFN-28(4x5) |
| Category | Others |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (VIN) | VIN | 8 | 100 | V | 3 | ||
| Input voltage (VREG) | VREG | 8.5 | 14 | V | 3 | ||
| OCREF voltage (VOC) | VOC | 0.125 | 2.4 | V | 3 | ||
| Operating junction temp. (TJ) | TJ | -40 | 125 | °C | 3 | ||
| Input voltage (VIN) | VIN | -0.3 | 110 | V | 3 | ||
| Input voltage VREG, GLA/B/C | -0.3 | 14.5 | V | 3 | |||
| LDO | -0.3 | 14.5 | V | 3 | |||
| BSTA/B/C | -0.3 | 120 | V | 3 | |||
| GHA/B/C | -0.3 | V | Printed max is (BST-SH) + 0.3 V, not a fixed number | 3 | |||
| GHA/B/C (transient) | -8 | V | transient, 2µs; printed max is (BST-SH) + 0.3 V, not a fixed number | 3 | |||
| LSS | -0.3 | 4 | V | 3 | |||
| LSS (transient) | -1 | 4 | V | transient, 2µs | 3 | ||
| SHA/B/C | -5 | 110 | V | 3 | |||
| SHA/B/C (transient) | -8 | 110 | V | transient, 2µs | 3 | ||
| All other pins to GND | -0.3 | 6.5 | V | 3 | |||
| Continuous power dissipation, QFN-28 (4mmx5mm) | PD | 3.1 | W | TA = +25°C | 3 | ||
| Storage temperature | -55 | 150 | °C | 3 | |||
| Junction temperature | 150 | °C | 3 | ||||
| Lead temperature (solder) | 260 | °C | 3 | ||||
| Input supply voltage | VIN | 8 | 100 | V | 4 | ||
| LDO output voltage | VLDO | 10.8 | 12 | 13.2 | V | ILDO ≤ 5mA, VIN > 15V | 4 |
| Gate driver supply voltage | VREG | 8.5 | 14 | V | 4 | ||
| Logic input current (high) | IIN(H) | -2.4 | 2.4 | µA | VIH = 0.8V | 4 | |
| Logic input current (low) | IIN(L) | -14 | 14 | µA | VIL = 5V | 4 | |
| HS gate drive pull-down resistance | RHS-DN | 0.6 | 4.5 | Ω | VDS = 1V | 4 | |
| LS gate drive pull-down resistance | RLS-DN | 0.6 | 4.5 | Ω | VDS = 1V | 4 | |
| VREG UVLO rising threshold | VREG_RUVLO | 6.5 | 7.5 | 8.5 | V | 4 | |
| VREG UVLO falling threshold | VREG_FUVLO | 6 | 6.8 | 7.6 | V | 4 | |
| VIN UVLO rising threshold | VVIN_RUVLO | 3.6 | 4 | 4.4 | V | 4 | |
| VIN UVLO falling threshold | VVIN_FUVLO | 3.4 | 3.8 | 4.3 | V | 4 | |
| OCREF threshold | VOC | 0.8 | 1 | 1.2 | V | VOC = 1V | 4 |
| OCREF threshold | VOC | 2.18 | 2.4 | 2.62 | V | VOC = 2.4V | 4 |
| Thermal resistance, junction-to-ambient, QFN-28 (4mmx5mm) | θJA | 40 | °C/W | Measured on JESD51-7, 4-layer PCB | 3 | ||
| Thermal resistance, junction-to-case, QFN-28 (4mmx5mm) | θJC | 9 | °C/W | 3 | |||
| Quiescent current | IQ | 0.7 | mA | nSLEEP = 1, not switching | 4 | ||
| Sleep mode supply current | ISLEEP | 1 | µA | nSLEEP = 0 | 4 | ||
| Input logic low threshold | VIL | 0.8 | V | 4 | |||
| Input logic high threshold | VIH | 2 | V | 4 | |||
| nSLEEP pull-down resistance | RSLEEP-PD | 450 | kΩ | 4 | |||
| Internal pull down resistance | RPD | 450 | kΩ | 4 | |||
| Output low voltage (fault output) | VOL | 0.1 | V | IO = 5mA | 4 | ||
| Output high leakage current (fault output) | IOH | 1 | µA | VO = 3.3V | 4 | ||
| VREG UVLO hysteresis | VREG_HYS | 610 | mV | 4 | |||
| VIN UVLO hysteresis | VVIN_HYS | 100 | mV | 4 | |||
| VBST UVLO threshold | VBST_UVLO | 4 | V | Voltage between SHx and BSTx | 4 | ||
| OCP deglitch time | tOC | 2.7 | µs | 4 | |||
| Sleep wake-up time | tSLEEP | 2 | ms | 4 | |||
| Thermal shutdown | TTSD | 175 | °C | Guaranteed by design (note 5) | 4 | ||
| Thermal shutdown hysteresis | TTSD_HYS | 20 | °C | Guaranteed by design (note 5) | 4 | ||
| Bootstrap diode forward voltage | VFBOOT | 1.2 | V | ID = 10mA | 4 | ||
| Bootstrap diode forward voltage | VFBOOT | 2.3 | V | ID = 50mA | 4 | ||
| Maximum source current | DSO | 0.8 | A | Guaranteed by design (note 5) | 4 | ||
| Maximum sink current | DSI | 1 | A | Guaranteed by design (note 5) | 4 | ||
| Gate drive pull-up resistance | RUP | 7 | Ω | VDS = 1V | 4 | ||
| LS automatic turn-on time | tLS | 4.6 | µs | 4 | |||
| Dead time | tDEAD | 560 | ns | RDT = 10kΩ | 4 | ||
| Dead time | tDEAD | 4.5 | µs | RDT = 100kΩ | 4 | ||
| Dead time | tDEAD | 77 | ns | DT tied to GND | 4 |
CAD (KiCad official)
- Symbol:
MP6539GV-Z - Footprint:
Package_DFN_QFN:QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm - 3D model: QFN-28(4x5) (KiCad packages3D, STEP)
- 3D model files:
mp6539gv-z-etched.step/mp6539gv-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp6539gv-z.step/mp6539gv-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems datasheet (15 pp, sha256
409284a676a5ee03, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MP6539GV-Z
**Monolithic Power Systems** · Others · QFN-28(4x5)
MP6539GV-Z from Monolithic Power Systems, in a QFN-28(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference for the device; the exposed pad on the backside is also connected to GND. |
| 2 | VIN | power_in | Input supply voltage with a recommended operating range of +8V to 100V. |
| 3 | CSO | output | Current sense output and OCP off-time adjust; requires at least 1nF from CSO to ground for stability. |
| 4 | LDO | power_out | Gate drive LDO output that connects directly to VREG for currents up to about 5mA, or drives the base of an external NPN for higher current. |
| 5 | VREG | power_in | Gate driver supply voltage with a recommended operating range of 8.5V to 14V. |
| 6 | BSTA | power_out | Bootstrap output for phase A, with a bootstrap capacitor connected between SHA and BSTA and an absolute maximum of 120V. |
| 7 | SHA | passive | High-side source connection for phase A, which is the bootstrap capacitor reference node. |
| 8 | GHA | output | High-side gate drive output for phase A, driving the HS-FET gate with a 0.8A source and 1A sink capability. |
| 9 | GLA | output | Low-side gate drive output for phase A, driving the LS-FET gate with a 0.8A source and 1A sink capability. |
| 10 | BSTB | power_out | Bootstrap output for phase B, with a bootstrap capacitor connected between SHB and BSTB and an absolute maximum of 120V. |
| 11 | SHB | passive | High-side source connection for phase B, which is the bootstrap capacitor reference node. |
| 12 | GHB | output | High-side gate drive output for phase B, driving the HS-FET gate with a 0.8A source and 1A sink capability. |
| 13 | GLB | output | Low-side gate drive output for phase B, driving the LS-FET gate with a 0.8A source and 1A sink capability. |
| 14 | BSTC | power_out | Bootstrap output for phase C, with a bootstrap capacitor connected between SHC and BSTC and an absolute maximum of 120V. |
| 15 | SHC | passive | High-side source connection for phase C, which is the bootstrap capacitor reference node. |
| 16 | GHC | output | High-side gate drive output for phase C, driving the HS-FET gate with a 0.8A source and 1A sink capability. |
| 17 | GLC | output | Low-side gate drive output for phase C, driving the LS-FET gate with a 0.8A source and 1A sink capability. |
| 18 | LSS | passive | Low-side source connection to the shared current sense resistor; absolute maximum rating is -0.3V to 4V. |
| 19 | LSC | input | Phase C low-side input pin that controls the LS-FET gate together with HSC per the input logic truth table. |
| 20 | LSB | input | Phase B low-side input pin that controls the LS-FET gate together with HSB per the input logic truth table. |
| 21 | LSA | input | Phase A low-side input pin that controls the LS-FET gate together with HSA per the input logic truth table. |
| 22 | HSC | input | Phase C high-side input pin that controls the HS-FET gate together with LSC per the input logic truth table. |
| 23 | HSB | input | Phase B high-side input pin that controls the HS-FET gate together with LSB per the input logic truth table. |
| 24 | HSA | input | Phase A high-side input pin that controls the HS-FET gate together with LSA per the input logic truth table. |
| 25 | nFAULT | output | Open-drain fault indication output that is driven logic low during a fault condition such as OCP or over-temperature. |
| 26 | nSLEEP | input | Sleep mode input where logic low enters low-power sleep and logic high enables the device, with an internal 450kΩ pulldown. |
| 27 | OCREF | input | Over-current protection reference input with a recommended voltage range of 0.125V to 2.4V. |
| 28 | DT | passive | Dead-time setting pin where a resistor to GND sets dead time per tDEAD = 0.044×R(kΩ) + 0.1 µs, and tying DT to GND applies the internal minimum. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | QFN-28(4x5) |
| Category | Others |
| Pins | 29 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (VIN) | VIN | 8 | | 100 | V | | 3 |
| Input voltage (VREG) | VREG | 8.5 | | 14 | V | | 3 |
| OCREF voltage (VOC) | VOC | 0.125 | | 2.4 | V | | 3 |
| Operating junction temp. (TJ) | TJ | -40 | | 125 | °C | | 3 |
| Input voltage (VIN) | VIN | -0.3 | | 110 | V | | 3 |
| Input voltage VREG, GLA/B/C | | -0.3 | | 14.5 | V | | 3 |
| LDO | | -0.3 | | 14.5 | V | | 3 |
| BSTA/B/C | | -0.3 | | 120 | V | | 3 |
| GHA/B/C | | -0.3 | | | V | Printed max is (BST-SH) + 0.3 V, not a fixed number | 3 |
| GHA/B/C (transient) | | -8 | | | V | transient, 2µs; printed max is (BST-SH) + 0.3 V, not a fixed number | 3 |
| LSS | | -0.3 | | 4 | V | | 3 |
| LSS (transient) | | -1 | | 4 | V | transient, 2µs | 3 |
| SHA/B/C | | -5 | | 110 | V | | 3 |
| SHA/B/C (transient) | | -8 | | 110 | V | transient, 2µs | 3 |
| All other pins to GND | | -0.3 | | 6.5 | V | | 3 |
| Continuous power dissipation, QFN-28 (4mmx5mm) | PD | | | 3.1 | W | TA = +25°C | 3 |
| Storage temperature | | -55 | | 150 | °C | | 3 |
| Junction temperature | | | | 150 | °C | | 3 |
| Lead temperature (solder) | | | | 260 | °C | | 3 |
| Input supply voltage | VIN | 8 | | 100 | V | | 4 |
| LDO output voltage | VLDO | 10.8 | 12 | 13.2 | V | ILDO ≤ 5mA, VIN > 15V | 4 |
| Gate driver supply voltage | VREG | 8.5 | | 14 | V | | 4 |
| Logic input current (high) | IIN(H) | -2.4 | | 2.4 | µA | VIH = 0.8V | 4 |
| Logic input current (low) | IIN(L) | -14 | | 14 | µA | VIL = 5V | 4 |
| HS gate drive pull-down resistance | RHS-DN | 0.6 | | 4.5 | Ω | VDS = 1V | 4 |
| LS gate drive pull-down resistance | RLS-DN | 0.6 | | 4.5 | Ω | VDS = 1V | 4 |
| VREG UVLO rising threshold | VREG_RUVLO | 6.5 | 7.5 | 8.5 | V | | 4 |
| VREG UVLO falling threshold | VREG_FUVLO | 6 | 6.8 | 7.6 | V | | 4 |
| VIN UVLO rising threshold | VVIN_RUVLO | 3.6 | 4 | 4.4 | V | | 4 |
| VIN UVLO falling threshold | VVIN_FUVLO | 3.4 | 3.8 | 4.3 | V | | 4 |
| OCREF threshold | VOC | 0.8 | 1 | 1.2 | V | VOC = 1V | 4 |
| OCREF threshold | VOC | 2.18 | 2.4 | 2.62 | V | VOC = 2.4V | 4 |
| Thermal resistance, junction-to-ambient, QFN-28 (4mmx5mm) | θJA | | 40 | | °C/W | Measured on JESD51-7, 4-layer PCB | 3 |
| Thermal resistance, junction-to-case, QFN-28 (4mmx5mm) | θJC | | 9 | | °C/W | | 3 |
| Quiescent current | IQ | | 0.7 | | mA | nSLEEP = 1, not switching | 4 |
| Sleep mode supply current | ISLEEP | | 1 | | µA | nSLEEP = 0 | 4 |
| Input logic low threshold | VIL | | 0.8 | | V | | 4 |
| Input logic high threshold | VIH | | 2 | | V | | 4 |
| nSLEEP pull-down resistance | RSLEEP-PD | | 450 | | kΩ | | 4 |
| Internal pull down resistance | RPD | | 450 | | kΩ | | 4 |
| Output low voltage (fault output) | VOL | | 0.1 | | V | IO = 5mA | 4 |
| Output high leakage current (fault output) | IOH | | 1 | | µA | VO = 3.3V | 4 |
| VREG UVLO hysteresis | VREG_HYS | | 610 | | mV | | 4 |
| VIN UVLO hysteresis | VVIN_HYS | | 100 | | mV | | 4 |
| VBST UVLO threshold | VBST_UVLO | | 4 | | V | Voltage between SHx and BSTx | 4 |
| OCP deglitch time | tOC | | 2.7 | | µs | | 4 |
| Sleep wake-up time | tSLEEP | | 2 | | ms | | 4 |
| Thermal shutdown | TTSD | | 175 | | °C | Guaranteed by design (note 5) | 4 |
| Thermal shutdown hysteresis | TTSD_HYS | | 20 | | °C | Guaranteed by design (note 5) | 4 |
| Bootstrap diode forward voltage | VFBOOT | | 1.2 | | V | ID = 10mA | 4 |
| Bootstrap diode forward voltage | VFBOOT | | 2.3 | | V | ID = 50mA | 4 |
| Maximum source current | DSO | | 0.8 | | A | Guaranteed by design (note 5) | 4 |
| Maximum sink current | DSI | | 1 | | A | Guaranteed by design (note 5) | 4 |
| Gate drive pull-up resistance | RUP | | 7 | | Ω | VDS = 1V | 4 |
| LS automatic turn-on time | tLS | | 4.6 | | µs | | 4 |
| Dead time | tDEAD | | 560 | | ns | RDT = 10kΩ | 4 |
| Dead time | tDEAD | | 4.5 | | µs | RDT = 100kΩ | 4 |
| Dead time | tDEAD | | 77 | | ns | DT tied to GND | 4 |
## CAD (KiCad official)
- Symbol: `MP6539GV-Z`
- Footprint: `Package_DFN_QFN:QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm`
- 3D model: QFN-28(4x5) (KiCad packages3D, STEP)
- 3D model files: `mp6539gv-z-etched.step` / `mp6539gv-z-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mp6539gv-z.step` / `mp6539gv-z.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Monolithic Power Systems datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602748243168686080) (15 pp, sha256 `409284a676a5ee03`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mp6539gv-z-datasheet.pdf)