component
MP6538GV-Z
Public Made by Adomby adom
MPS(芯源) , QFN-28(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MP6538GV-Z
MPS(芯源) · IC · QFN-28(4x5)
MP6538GV-Z from MPS(芯源), in a QFN-28(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin for the device. |
| 2 | VIN | power_in | Input supply voltage, recommended +8V to 100V with an absolute maximum of 110V. |
| 3 | CSO | output | Current-sense amplifier output that amplifies the LSS voltage by 20 and needs at least 1nF from CSO to ground for stability; it also sets the OCP off time. |
| 4 | LDO | power_out | Gate-drive LDO output that also serves as the base drive for an external NPN transistor when more than about 5mA is needed. |
| 5 | VREG | power_in | Gate driver supply voltage, recommended +8.5V to 14V, with an absolute maximum of 14.5V. |
| 6 | BSTA | power_out | Bootstrap output for phase A, rated for -0.3V to 120V. |
| 7 | SHA | passive | High-side source connection for phase A, rated for -5V to 110V. |
| 8 | GHA | output | High-side gate drive output for phase A, limited to (BST-SH) + 0.3V. |
| 9 | GLA | output | Low-side gate drive output for phase A, rated for -0.3V to 14.5V. |
| 10 | BSTB | power_out | Bootstrap output for phase B, rated for -0.3V to 120V. |
| 11 | SHB | passive | High-side source connection for phase B, rated for -5V to 110V. |
| 12 | GHB | output | High-side gate drive output for phase B, limited to (BST-SH) + 0.3V. |
| 13 | GLB | output | Low-side gate drive output for phase B, rated for -0.3V to 14.5V. |
| 14 | BSTC | power_out | Bootstrap output for phase C, rated for -0.3V to 120V. |
| 15 | SHC | passive | High-side source connection for phase C, rated for -5V to 110V. |
| 16 | GHC | output | High-side gate drive output for phase C, limited to (BST-SH) + 0.3V. |
| 17 | GLC | output | Low-side gate drive output for phase C, rated for -0.3V to 14.5V. |
| 18 | LSS | passive | Low-side source connection that feeds the current-sense amplifier; rated for -0.3V to 4V (-1V to 4V for 2µs transients). |
| 19 | HC | input | Phase C Hall-sensor input, which is one of three Hall inputs spaced at 120° for commutation. |
| 20 | HB | input | Phase B Hall-sensor input, which is one of three Hall inputs spaced at 120° for commutation. |
| 21 | HA | input | Phase A Hall-sensor input, which is one of three Hall inputs spaced at 120° for commutation. |
| 22 | nBRAKE | input | Active-low brake input; when low, all low-side gates are turned on, with logic thresholds VIL 0.8V max and VIH 2V min. |
| 23 | PWM | input | External PWM input for speed and torque control, with logic thresholds VIL 0.8V max and VIH 2V min. |
| 24 | DIR | input | Logic input that determines the direction of the motor torque output. |
| 25 | nFAULT | output | Open-drain fault output that is driven low during an OCP, over-temperature or UVLO-related fault condition, with VOL of 0.1V max at 5mA. |
| 26 | nSLEEP | input | Sleep mode input where logic low enters low-power sleep and high enables the device, with an internal 450kΩ pull-down. |
| 27 | OCREF | input | Over-current protection reference input, with a recommended range of 0.125V to 2.4V. |
| 28 | DT | passive | Dead-time setting pin where a resistor from DT to GND sets tDEAD = 0.044×R(kΩ) + 0.1 µs. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MPS(芯源) |
| Package | QFN-28(4x5) |
| Category | |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (VIN) | VIN | -0.3 | 110 | V | 3 | ||
| Input voltage VREG, GLA/B/C | -0.3 | 14.5 | V | 3 | |||
| LDO | -0.3 | 14.5 | V | 3 | |||
| BSTA/B/C | -0.3 | 120 | V | 3 | |||
| GHA/B/C | -0.3 | V | max printed as (BST-SH) + 0.3V | 3 | |||
| GHA/B/C transient | -8 | V | transient 2µs; max printed as (BST-SH) + 0.3V | 3 | |||
| LSS | -0.3 | 4 | V | 3 | |||
| LSS transient | -1 | 4 | V | transient 2µs | 3 | ||
| SHA/B/C | -5 | 110 | V | 3 | |||
| SHA/B/C transient | -8 | 110 | V | transient 2µs | 3 | ||
| All other pins to GND | -0.3 | 6.5 | V | 3 | |||
| Continuous power dissipation QFN-28 (4mmx5mm) | 3.1 | W | TA = +25°C | 3 | |||
| Storage temperature | -55 | 150 | °C | 3 | |||
| Junction temperature | 150 | °C | 3 | ||||
| Lead temperature (solder) | 260 | °C | 3 | ||||
| Input voltage (VIN) | VIN | 8 | 100 | V | 3 | ||
| Input voltage (VREG) | VREG | 8.5 | 14 | V | 3 | ||
| OCREF voltage (VOC) | VOC | 0.125 | 2.4 | V | 3 | ||
| Operating junction temp (TJ) | TJ | -40 | 125 | °C | 3 | ||
| Input supply voltage | VIN | 8 | 100 | V | 4 | ||
| LDO output voltage | VLDO | 10.8 | 12 | 13.2 | V | ILDO ≤ 5mA, VIN > 15V | 4 |
| Gate driver supply voltage | VREG | 8.5 | 14 | V | 4 | ||
| Logic input current high | IIN(H) | -2.4 | 2.4 | µA | VIH = 0.8V | 4 | |
| Logic input current low | IIN(L) | -14 | 14 | µA | VIL = 5V | 4 | |
| VREG UVLO rising threshold | VREG_RUVLO | 6.5 | 7.5 | 8.5 | V | 4 | |
| VREG UVLO falling threshold | VREG_FUVLO | 6 | 6.8 | 7.6 | V | 4 | |
| VIN UVLO rising threshold | VVIN_RUVLO | 3.6 | 4 | 4.4 | V | 4 | |
| VIN UVLO falling threshold | VVIN_FUVLO | 3.4 | 3.8 | 4.3 | V | 4 | |
| OCREF threshold | VOC | 0.8 | 1 | 1.2 | V | VOC = 1V | 4 |
| OCREF threshold | VOC | 2.18 | 2.4 | 2.62 | V | VOC = 2.4V | 4 |
| HS gate drive pull-down resistance | RHS-DN | 0.6 | 4.5 | Ω | VDS = 1V | 4 | |
| LS gate drive pull-down resistance | RLS-DN | 0.6 | 4.5 | Ω | VDS = 1V | 4 | |
| Quiescent current (nSLEEP=1) | IQ | 0.7 | mA | nSLEEP = 1, not switching | 4 | ||
| Sleep current | ISLEEP | 1 | µA | nSLEEP = 0 | 4 | ||
| Input logic low threshold | VIL | 0.8 | V | 4 | |||
| Input logic high threshold | VIH | 2 | V | 4 | |||
| nSLEEP pull-down resistance | RSLEEP-PD | 450 | kΩ | 4 | |||
| Internal pull-down resistance | RPD | 450 | kΩ | 4 | |||
| Output low voltage (fault output) | VOL | 0.1 | V | IO = 5mA | 4 | ||
| Output high leakage current (fault output) | IOH | 1 | µA | VO = 3.3V | 4 | ||
| VREG UVLO hysteresis | VREG_HYS | 610 | mV | 4 | |||
| VIN UVLO hysteresis | VVIN_HYS | 100 | mV | 4 | |||
| VBST UVLO threshold | VBST_UVLO | 4 | V | Voltage between SHx and BSTx | 4 | ||
| OCP deglitch time | tOC | 2.7 | µs | 4 | |||
| Sleep wake-up time | tSLEEP | 2 | ms | 4 | |||
| Thermal shutdown | TTSD | 175 | °C | Guaranteed by design (note 5) | 4 | ||
| Thermal shutdown hysteresis | TTSD_HYS | 20 | °C | Guaranteed by design (note 5) | 4 | ||
| Bootstrap diode forward voltage | VFBOOT | 1.2 | V | ID = 10mA | 4 | ||
| Bootstrap diode forward voltage | VFBOOT | 2.3 | V | ID = 50mA | 4 | ||
| Maximum source current | DSO | 0.8 | A | Guaranteed by design (note 5) | 4 | ||
| Maximum sink current | DSI | 1 | A | Guaranteed by design (note 5) | 4 | ||
| Gate drive pull-up resistance | RUP | 7 | Ω | VDS = 1V | 4 | ||
| LS automatic turn-on time | tLS | 4.6 | µs | 4 | |||
| Dead time | tDEAD | 560 | ns | RDT = 10kΩ | 4 | ||
| Dead time | tDEAD | 4.5 | µs | RDT = 100kΩ | 4 | ||
| Dead time | tDEAD | 77 | ns | DT tied to GND | 4 | ||
| Thermal resistance junction-to-ambient | θJA | 40 | °C/W | Measured on JESD51-7, 4-layer PCB (note 4) | 3 | ||
| Thermal resistance junction-to-case | θJC | 9 | °C/W | Measured on JESD51-7, 4-layer PCB (note 4) | 3 |
CAD (KiCad official)
- Symbol:
MP6538GV-Z - Footprint:
Package_DFN_QFN:QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm - 3D model: QFN-28(4x5) (KiCad packages3D, STEP)
- 3D model files:
mp6538gv-z-etched.step/mp6538gv-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp6538gv-z.step/mp6538gv-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MPS(芯源) datasheet (14 pp, sha256
420e9bf2c6fc49c3, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).