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MP6536DU-LF-Z

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Monolithic Power Systems Brushless DC (BLDC) Motor Driver, QFN-40(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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MP6536DU-LF-Z

Monolithic Power Systems · Brushless DC (BLDC) Motor Driver · QFN-40(5x5)

MP6536DU-LF-Z from Monolithic Power Systems, in a QFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW2 output Output 2. SW2 is valid approximately 100µs after VSP goes high.
2 SW2 output Output 2. SW2 is valid approximately 100µs after VSP goes high.
3 VSP power_in Power Supply Input; connect VSP to positive side of input power supply. Bypass VSP to PGND as close to IC as possible.
4 VSP power_in Power Supply Input; connect VSP to positive side of input power supply. Bypass VSP to PGND as close to IC as possible.
5 VSP power_in Power Supply Input; connect VSP to positive side of input power supply. Bypass VSP to PGND as close to IC as possible.
6 SW1 output Output 1. SW1 is valid approximately 100µs after VSP goes high.
7 SW1 output Output 1. SW1 is valid approximately 100µs after VSP goes high.
8 LS1 passive Low-Side Source Connection of SW1.
9 LS1 passive Low-Side Source Connection of SW1.
10 BST1 passive Bootstrap Supply for high-side gate drive of SW1 stage; connect 0.1μF or greater capacitor between BST1 and SW1.
11 NC unconnected No Connection. NC MUST be kept floating.
12 PWM1 input Driver Logic Input 1; drive PWM high to turn on high-side switch, low to turn on low-side switch.
13 PWM2 input Driver Logic Input 2; drive PWM high to turn on high-side switch, low to turn on low-side switch.
14 FAULTB tri_state Fault Output; low output indicates over-temperature, over-current, or under-voltage condition. Open-drain output.
15 SHDNB input Shutdown Input; when SHDNB is low, the IC shuts off.
16 PWM3 input Driver Logic Input 3; drive PWM high to turn on high-side switch, low to turn on low-side switch.
17 STBYB input Standby Input; default low (internal pull-down). If driven high, output determined by PWM1/2/3. If low, all outputs high impedance.
18 AGND power_in Analog Ground.
19 FLT3B tri_state Fault Monitor for channel 3; active low open-drain output.
20 FLT2B tri_state Fault Monitor for channel 2; active low open-drain output.
21 NC unconnected No Connection. NC MUST be kept floating.
22 PGND power_in Power Ground; connect exposed pad on bottom side to ground plane.
23 PGND power_in Power Ground; connect exposed pad on bottom side to ground plane.
24 NC unconnected No Connection. NC MUST be kept floating.
25 NC unconnected No Connection. NC MUST be kept floating.
26 VSP power_in Power Supply Input; connect VSP to positive side of input power supply. Bypass VSP to PGND as close to IC as possible.
27 VSP power_in Power Supply Input; connect VSP to positive side of input power supply. Bypass VSP to PGND as close to IC as possible.
28 VSP power_in Power Supply Input; connect VSP to positive side of input power supply. Bypass VSP to PGND as close to IC as possible.
29 SW3 output Output 3. SW3 is valid approximately 100µs after VSP goes high.
30 SW3 output Output 3. SW3 is valid approximately 100µs after VSP goes high.
31 LS3 passive Low-Side Source Connection of SW3.
32 LS3 passive Low-Side Source Connection of SW3.
33 BST3 passive Bootstrap Supply for high-side gate drive of SW3 stage; connect 0.1μF or greater capacitor between BST3 and SW3.
34 VDR2 output Gate Drive Supply Bypass from internal regulator; powers internal circuitry and gate drive for SW3 stage. Bypass VDR2 to PGND with 0.1μF to 10μF capacitor.
35 AGND power_in Analog Ground.
36 AGND power_in Analog Ground.
37 VDR1 output Gate Drive Supply Bypass from internal regulator; powers internal circuitry and gate drive for SW1 and SW2 stages. Bypass VDR1 to PGND with 0.1μF to 10μF capacitor.
38 BST2 passive Bootstrap Supply for high-side gate drive of SW2 stage; connect 0.1μF or greater capacitor between BST2 and SW2.
39 LS2 passive Low-Side Source Connection of the SW2.
40 LS2 passive Low-Side Source Connection of the SW2.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Monolithic Power Systems
Package QFN-40(5x5)
Category Motor Driver ICs
Pins 41

CAD (KiCad official)

  • Symbol: MP6536DU-LF-Z
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40(5x5) (KiCad packages3D, STEP)
  • 3D model files: mp6536du-lf-z-etched.step / mp6536du-lf-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp6536du-lf-z.step / mp6536du-lf-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Monolithic Power Systems datasheet (10 pp, sha256 0161c9c916500ff9, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF