# MP6400DJ-33-LF-Z

**Monolithic Power Systems** · Supervisor And Reset ICs · TSOT-23-6

MP6400DJ-33-LF-Z from Monolithic Power Systems, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | output | Open-drain reset output that is asserted when SENSE falls below VIT or MR is pulled low, and requires a pull-up resistor bigger than 10 kΩ to the supply, which may be pulled up above VCC (up to 6 V); the absolute maximum RESET current is 5 mA. |
| 2 | GND | power_in | Ground reference for the device. |
| 3 | MR | input | Manual reset input that is internally pulled up to VCC through a 90 kΩ resistor, and a logic low (VIL max 0.25 VCC) asserts RESET while logic high (VIH min 0.7 VCC) is required for normal operation. |
| 4 | CDELAY | passive | Reset delay programming pin: connecting it to VCC through a 50 kΩ to 200 kΩ resistor selects 380 ms, leaving it floating selects 24 ms, and a capacitor larger than 150 pF to GND gives a programmable delay from 2.1 ms to 10 s. |
| 5 | SENSE | input | Monitored system voltage input where RESET is asserted when the voltage falls below the threshold VIT, with absolute maximum rating of -0.3 V to 6 V. |
| 6 | VCC | power_in | Supply voltage input with a recommended operating range of 1.8 V to 6 V, which should be decoupled with a 0.1 µF ceramic capacitor placed close to the pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | TSOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Range | VCC | 1.8 |  | 6 | V |  | 4 |
| Supply Current (current into VCC pin) | ICC |  | 1.6 | 3.5 | µA | VCC = 3.3V, RESET not asserted, MR, RESET, CDELAY open | 4 |
| Supply Current (current into VCC pin) | ICC |  | 1.85 | 12 | µA | VCC = 6V, RESET not asserted, MR, RESET, CDELAY open | 4 |
| Low-level Output Voltage | VOL |  |  | 0.3 | V | 1.3V ≤ VCC < 1.8V, IOL = 0.4mA | 4 |
| Low-level Output Voltage | VOL |  |  | 0.4 | V | 1.8V ≤ VCC ≤ 6V, IOL = 1.0mA | 4 |
| Power-up Reset Voltage |  |  |  | 0.8 | V | VOL (max) = 0.2V, IRESET = 15µA, Trise(VCC) ≥ 15µs/V | 4 |
| Negative-going Input Threshold Accuracy | VIT | -2 | 1 | 2 | % | VSENSE falling slowly; typ printed as ±1.0% | 4 |
| Hysteresis on VIT Pin | VHYS | 1.5 |  | 3.5 | VIT% |  | 4 |
| MR Internal Pull-up Resistance | R | 50 |  | 110 | kΩ |  | 4 |
| Input Current at SENSE Pin (fixed versions) | ISENSE |  |  | 2.4 | µA | Fixed versions, VSENSE = 6V | 4 |
| RESET Leakage Current |  |  |  | 300 | nA | RESET V = 6V, RESET not asserted | 4 |
| MR Logic Low Input | VIL |  |  | 0.25 | VCC | Printed as 0.25VCC | 4 |
| MR Logic High Input | VIH | 0.7 |  |  | VCC | Printed as 0.7VCC | 4 |
| SENSE Maximum Transient Duration | tw |  |  | 17.5 | µs | VIH = 1.05 VIT, VIL = 0.95 VIT | 4 |
| RESET Delay Time (CDELAY open) | td | 15 | 24 | 34 | ms | CDELAY = Open | 4 |
| RESET Delay Time (CDELAY = VCC) | td | 230 | 380 | 530 | ms | CDELAY = VCC | 4 |
| RESET Delay Time (CDELAY = 150pF) | td | 1.3 | 2.1 | 3 | ms | CDELAY = 150pF | 4 |
| RESET Delay Time (CDELAY = 10nF) | td | 61 | 102 | 142 | ms | CDELAY = 10nF | 4 |
| MR to RESET Propagation Delay High to Low | tpHL1 |  |  | 160 | ns | VIH = 0.7 VCC, VIL = 0.25 VCC | 4 |
| SENSE to RESET Propagation Delay High to Low | tpHL2 |  |  | 17.5 | µs | VIH = 1.05 VIT, VIL = 0.95 VIT | 4 |
| Supply Voltage VCC (absolute maximum) | VCC | -0.3 |  | 6.5 | V |  | 3 |
| CDELAY Voltage | VCDELAY | -0.3 |  |  | V | Maximum printed as VCC + 0.3V | 3 |
| SENSE Voltage | VSENSE | -0.3 |  | 6 | V |  | 3 |
| All Other Pins Voltage |  | -0.3 |  | 6.5 | V |  | 3 |
| RESET Current | IRESET |  |  | 5 | mA |  | 3 |
| Junction Temperature | TJ |  |  | 150 | °C |  | 3 |
| Storage Temperature | TSTG | -65 |  | 150 | °C |  | 3 |
| Recommended Supply Voltage | VCC | 1.8 |  | 6 | V |  | 3 |
| Operating Junction Temperature | TJ | -40 |  | 125 | °C |  | 3 |
| Threshold Voltage (VIT) for 3.3V nominal version | VIT |  | 3.07 |  | V | Nominal supply 3.3V, MP6400DJ-33 | 5 |
| Thermal Resistance Junction-to-Case TSOT23-6 | θJC |  | 110 |  | °C/W | Measured on JESD51-7 4-layer board | 3 |

## CAD (KiCad official)

- Symbol: `MP6400DJ-33-LF-Z`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-6`
- 3D model: TSOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `mp6400dj-33-lf-z-etched.step` / `mp6400dj-33-lf-z-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mp6400dj-33-lf-z.step` / `mp6400dj-33-lf-z.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Monolithic Power Systems datasheet](docs/mp6400dj-33-lf-z-datasheet.pdf) (12 pp, sha256 `0d075db4e48b0d2d`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mp6400dj-33-lf-z-datasheet.pdf)