component
MP4541GN-Z
Public Made by Adomby adom
Monolithic Power Systems DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MP4541GN-Z
Monolithic Power Systems · DC-DC Converters · SOIC-8-EP
MP4541GN-Z from Monolithic Power Systems, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Power enable: pull high to turn on the MP4541 and low to turn it off; do not float the pin (rising threshold typ 1.25V, compatible with voltages up to 80V). |
| 2 | VCC | power_out | Internal LDO output that supplies the internal control circuit; decouple with a ≥1μF ceramic capacitor (regulation typ 4.85V at IVCC = 2mA). |
| 3 | FREQ | passive | Switching frequency setting pin; connect an external resistor from FREQ to GND to set the buck fSW (100kHz to 1MHz). |
| 4 | FB | input | Output voltage feedback; connect a resistor divider from the output to the FB pin (VREF typ 1V). |
| 5 | BST | passive | Bootstrap power for the high-side MOSFET gate driver; connect a 0.1μF capacitor between the BST and SW pins. |
| 6 | SW | output | Switch node of the converter, connected to the source of the HS-FET and the drain of the LS-FET (-0.5V to +85V absolute maximum). |
| 7 | GND | power_in | Power ground. |
| 8 | VIN | power_in | Power supply input, 8V to 80V recommended operating range (85V absolute maximum). |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | SOIC-8-EP |
| Category | Power Supply Chip |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC UVLO threshold rising | VCCUVLO-R | 3.15 | 3.35 | 3.55 | V | VCC rising | 4 |
| VCC regulation voltage | 4.5 | 4.85 | 5.2 | V | IVCC = 2mA | 4 | |
| EN input high threshold | VEN_ON | 1.15 | 1.25 | 1.35 | V | VEN rising | 4 |
| FB reference voltage (25C) | VREF | 0.99 | 1 | 1.01 | V | 8V to 100V, TJ = 25°C | 4 |
| FB reference voltage (full temp) | VREF | 0.985 | 1 | 1.015 | V | 8V to 100V, TJ = -40°C to +125°C | 4 |
| LS-FET valley current limit (25C) | IVL_LIMT | 0.72 | 0.8 | 0.88 | A | Over full duty cycle, TJ = 25°C | 4 |
| LS-FET valley current limit (full temp) | IVL_LIMT | 0.68 | 0.8 | 0.92 | A | Over full duty cycle, TJ = -40°C to +125°C | 4 |
| Inductor current ZCD threshold | -60 | 0 | 60 | mA | 4 | ||
| Shutdown current | ISD | 2 | μA | VEN = 0V, measured on VIN | 4 | ||
| VCC UVLO threshold hysteresis | VCCHYS | 150 | mV | 4 | |||
| Quiescent current | IQ | 15 | μA | VIN = 12V, VFB = 1.05V, no switching, measured on VIN, TJ = 25°C | 4 | ||
| Micro-power EN start-up threshold | 0.9 | V | 4 | ||||
| Micro-power EN off threshold | 0.4 | V | 4 | ||||
| EN hysteresis | VEN_H | 120 | mV | VEN rising/falling | 4 | ||
| Minimum off time | tMIN_OFF | 150 | ns | VFB = 0V | 4 | ||
| Minimum on time | tMIN_ON | 45 | ns | 4 | |||
| FB input current | IFB | 50 | nA | VFB = 1.05V | 4 | ||
| Soft-start time | tSS | 4.35 | ms | 10% to 90% of VREF | 4 | ||
| FB under-voltage threshold | VUVP | 60 | % VREF | 4 | |||
| LS-FET on resistance | RON_L | 265 | mΩ | 4 | |||
| Synchronous HS-FET on resistance | RON_H | 625 | mΩ | 4 | |||
| Thermal shutdown | TSD | 150 | °C | 4 | |||
| Thermal shutdown hysteresis | TSD_HYS | 25 | °C | 4 | |||
| VIN, EN voltage | VIN, EN | -0.3 | 85 | V | 3 | ||
| SW voltage | SW | -0.5 | 85 | V | 3 | ||
| SW voltage (<20ns) | SW | -5 | 88 | V | <20ns | 3 | |
| BST to SW voltage | -0.3 | 6 | V | 3 | |||
| All other pins | -0.3 | 6 | V | 3 | |||
| Continuous power dissipation | 3.2 | W | TA = 25°C | 3 | |||
| Junction temperature | TJ | 150 | °C | 3 | |||
| Lead temperature | 260 | °C | 3 | ||||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Supply voltage | VIN | 8 | 80 | V | 3 | ||
| Output voltage | VOUT | 1 | 30 | V | 3 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 3 | ||
| Thermal resistance junction-ambient | θJA | 38 | °C/W | EV4541-N-00A | 3 | ||
| Thermal resistance junction-case | θJC | 7.5 | °C/W | EV4541-N-00A | 3 | ||
| Thermal resistance junction-ambient | θJA | 48 | °C/W | JESD51-7 | 3 | ||
| Thermal resistance junction-case | θJC | 10 | °C/W | JESD51-7 | 3 |
CAD (KiCad official)
- Symbol:
MP4541GN-Z - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
mp4541gn-z-etched.step/mp4541gn-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp4541gn-z.step/mp4541gn-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems datasheet (20 pp, sha256
5568fd28559b66d2, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).