component

MP4317GRE-Z

Public Made by Adom

by adom

Monolithic Power Systems DC-DC Converters, QFN-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)mp4317gre-zfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 15d ago
viewers mp4317gre-z: viewers · Ray 15d ago
mp4317gre-z-etched.glb Publish 0.1.0 · Ray 15d ago
mp4317gre-z-etched.step mp4317gre-z: factory component page (tier=lcsc) · Ray 15d ago
mp4317gre-z-hero.glb mp4317gre-z: hero GLB from the etched model (keeps the MPN mark) · Ray 15d ago
mp4317gre-z-hero.overlay.json Publish 0.1.0 · Ray 15d ago
mp4317gre-z.glb Publish 0.1.0 · Ray 15d ago
mp4317gre-z.kicad_mod Publish 0.1.0 · Ray 15d ago
mp4317gre-z.kicad_sym Publish 0.1.0 · Ray 15d ago
mp4317gre-z.lbr Publish 0.1.0 · Ray 15d ago
mp4317gre-z.step Publish 0.1.0 · Ray 15d ago
package.json Publish 0.1.0 · Ray 15d ago
page.json Set visibility: public · Ray 15d ago
README.md Publish 0.1.0 · Ray 15d ago

MP4317GRE-Z

Monolithic Power Systems · DC-DC Converters · QFN-20(4x4)

MP4317GRE-Z from Monolithic Power Systems, in a QFN-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MODE input Mode selection: pull high for forced continuous conduction mode (FCCM), pull low for advanced asynchronous modulation (AAM) mode; do not float.
2 SYNCIN input Synchronous input accepting a 350kHz to 1000kHz external clock; internally high impedance, place a ≤51kΩ resistor to AGND if the clock pull-down is insufficient, do not float.
3 VIN power_in Input supply powering the internal circuitry and the high-side MOSFET; decouple with a capacitor to PGND placed close to the pin.
4 PGND power_in Power ground.
5 PGND power_in Power ground.
6 BST passive Bootstrap positive supply for the HS-FET driver; connect a bypass capacitor between BST and SW.
7 SW output Switch output of the internal power MOSFETs.
8 SW output Switch output of the internal power MOSFETs.
9 EN input Enable: pull above 1V to turn the converter on, pull below 0.85V to turn it off.
10 PGND power_in Power ground.
11 PGND power_in Power ground.
12 VIN power_in Input supply powering the internal circuitry and the high-side MOSFET; decouple with a capacitor to PGND placed close to the pin.
13 SYNCO output Synchronous output clock 180° out of phase with the internal oscillator (or opposite to the SYNCIN clock); float if not used.
14 PG output Open-drain power good output, high between 95% and 105% of nominal VOUT and pulled low above 106.5% or below 93%; connect to a source via a pull-up resistor.
15 NC unconnected Not connected.
16 VCC power_out Bias supply providing 4.9V to the internal control circuit and gate drivers; decouple with a capacitor to AGND placed close to the pin.
17 AGND power_in Analog ground.
18 FB input Feedback input connected to the center of the external resistor divider setting VOUT; feedback threshold is 0.815V.
19 SS passive Soft-start input: a capacitor to AGND sets the soft-start time, with 13µA sourced into the soft-start capacitor during start-up.
20 FREQ passive Switching frequency setting: connect a resistor from FREQ to AGND to set fSW.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Monolithic Power Systems
Package QFN-20(4x4)
Category Power Management (PMIC)
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN UVLO rising threshold VIN_UVLO_RISING 2.8 3 3.2 V VIN = 12V, VEN = 2V, TJ = -40°C to +125°C 6
VIN UVLO falling threshold VIN_UVLO_FALLING 2.5 2.7 2.9 V 6
VCC voltage VCC 4.6 4.9 5.2 V IVCC = 0A 6
Quiescent current during sleep mode ISLEEP 18 26 μA VFB = 0.85V, sleep mode, no load 6
Shutdown current ISD 1.7 3.5 μA VEN = 0V 6
Feedback voltage VFB 807 815 823 mV VIN = 3.3V to 45V, TJ = 25°C 6
Feedback voltage over temperature VFB 799 815 831 mV VIN = 3.3V to 45V 6
FB current IFB -50 0 50 nA VFB = 0.85V 6
Switching frequency fSW 420 470 520 kHz RFREQ = 62kΩ 6
Switching frequency fSW 820 1000 1180 kHz RFREQ = 26.1kΩ 6
SYNCIN clock range fSYNC 350 1000 kHz External clock 6
SYNCO high voltage VSYNCO_HIGH 3.3 4.5 V ISYNCO = -1mA 6
SYNCO low voltage VSYNCO_LOW 0.4 V ISYNCO = 1mA 6
HS-FET peak current limit ILIMIT_PEAK 10 13 16 A 30% duty cycle 6
LS-FET valley current limit ILIMIT_VALLEY 8 10 12 A 6
Zero-current detection current IZCD -0.15 0.1 0.35 A AAM mode 6
LS-FET reverse current limit ILIMIT_REVERSE 2 4.5 7 A FCCM 6
Switch leakage current ISW_LKG 0.01 1 µA 6
HS-FET on resistance RDS(ON)_HS 48 80 mΩ VBST - VSW = 5V 6
LS-FET on resistance RDS(ON)_LS 20 40 mΩ VCC = 5V 6
Soft-start current ISS 8 13 19 µA VSS = 0V 6
EN rising threshold VEN_RISING 0.8 1 1.2 V 6
EN falling threshold VEN_FALLING 0.65 0.85 1.05 V 6
PG rising threshold (VFB rising) VPG_RISING 92 95 98 % of VREF VFB rising, VFB / VREF 7
PG rising threshold (VFB falling) VPG_RISING 102 105 108 % of VREF VFB falling, VFB / VREF 7
PG falling threshold (VFB falling) VPG_FALLING 90.5 93.5 96.5 % of VREF VFB falling, VFB / VREF 7
PG falling threshold (VFB rising) VPG_FALLING 103.5 106.5 109.5 % of VREF VFB rising, VFB / VREF 7
PG output voltage low VPG_LOW 0.1 0.3 V ISINK = 1mA 7
VIN UVLO hysteresis VIN_UVLO_HYS 280 mV 6
VCC regulation 1 4 % IVCC = 30mA 6
VCC current limit ILIMIT_VCC 100 mA VCC = 4V 6
Minimum on time tON_MIN 100 ns 6
Minimum off time tOFF_MIN 80 ns 6
SYNCIN voltage rising threshold VSYNC_RISING 1.8 V 6
SYNCIN voltage falling threshold VSYNC_FALLING 0.4 V 6
MODE rising threshold VMODE_RISING 1.8 V 7
MODE falling threshold VMODE_FALLING 0.4 V 7
PG rising delay tPG_DELAY_RISING 35 µs 7
PG falling delay tPG_DELAY_FALLING 35 µs 7
Thermal shutdown TSD 170 °C 7
Thermal shutdown hysteresis TSD_HYS 20 °C 7
Supply voltage VIN 3.3 45 V 5
Operating junction temperature TJ -40 125 °C 5
VIN, EN voltage -0.3 50 V 5
SW voltage -0.3 V upper limit VIN_MAX + 0.3V 5
All other pins -0.3 5.5 V 5
Operating junction temperature TJ 150 °C 5
Storage temperature -65 150 °C 5
ESD human body model -2 2 kV 5
ESD charged device model -750 750 V 5
Thermal resistance junction-case θJC 9 °C/W JESD51-7, QFN-20 (4mmx4mm) 5

CAD (KiCad official)

  • Symbol: MP4317GRE-Z
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20(4x4) (KiCad packages3D, STEP)
  • 3D model files: mp4317gre-z-etched.step / mp4317gre-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp4317gre-z.step / mp4317gre-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Monolithic Power Systems datasheet (38 pp, sha256 eab4f7e7704571d2, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF