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MP4315GRE-Z

Public Made by Adom

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Monolithic Power Systems DC-DC Converters, QFN-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MP4315GRE-Z

Monolithic Power Systems · DC-DC Converters · QFN-20(4x4)

MP4315GRE-Z from Monolithic Power Systems, in a QFN-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MODE input Selects forced continuous conduction mode (FCCM) when pulled high or advanced asynchronous mode (AAM) when pulled low under light loads, and must not be left floating.
2 SYNCIN input Accepts a 350kHz to 1000kHz clock to synchronize the internal oscillator and supports multi-phase operation; connect to GND if unused and do not float.
3 VIN power_in Input supply for the internal control circuitry and the power switch connected to SW, rated 3.3V to 45V, with a decoupling capacitor recommended from VIN to ground.
4 PGND power_in Power ground for the power stage.
5 PGND power_in Power ground for the power stage.
6 BST passive Bootstrap positive supply for the high-side MOSFET; a bypass capacitor must be connected between BST and SW, sized per the datasheet BST diode and resistor section.
7 SW output Switch node, the output of the internal power switch.
8 SW output Switch node, the output of the internal power switch.
9 EN input Enable input that shuts the device down when pulled below 0.85V and enables it when pulled above 1V.
10 PGND power_in Power ground for the power stage.
11 PGND power_in Power ground for the power stage.
12 VIN power_in Input supply for the internal control circuitry and the power switch connected to SW, rated 3.3V to 45V, with a decoupling capacitor recommended from VIN to ground.
13 SYNCO output Outputs a clock 180° out of phase with the internal oscillator (or the inverse of the SYNCIN clock); float if not used.
14 PG output Open-drain power good output that requires a pull-up resistor; it goes high when VOUT is within 93% to 106% of nominal and low when VOUT is above 107.5% or below 91%.
15 NC unconnected Not internally connected, but must be tied to VCC or the output (≥3V) and must not be left floating.
16 VCC power_out Bias supply that provides 4.9V to the internal control circuit and gate drivers, requiring a decoupling capacitor placed close to the pin.
17 AGND power_in Analog ground for the control circuitry.
18 FB input Feedback input connected to the center point of the external resistor divider, with a feedback threshold voltage of about 0.815V.
19 SS passive Soft-start input; a capacitor from SS to GND sets the soft-start time, as the MP4315 sources 6µA into it at start-up to limit inrush current.
20 FREQ input Switching frequency configuration; a resistor from this pin to GND sets fSW per the fSW vs. RFREQ curve in the datasheet.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Monolithic Power Systems
Package QFN-20(4x4)
Category Power Management (PMIC)
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN under-voltage lockout (UVLO) rising threshold INUVLO_RISING 2.8 3 3.2 V 6
VIN UVLO falling threshold INUVLO_FALLING 2.45 2.65 2.85 V 6
VCC voltage VCC 4.6 4.9 5.2 V IVCC = 0A 6
VCC regulation 1 4 % IVCC = 30mA 6
VIN quiescent current (sleep mode) IQ 18 26 μA VFB = 0.85V, no load, sleep mode 6
VIN shutdown current ISHDN 1.7 3.5 μA EN = 0V 6
FB voltage VFB 0.807 0.815 0.823 V VIN = 3.3V to 45V, TJ = 25°C 6
FB voltage VFB 0.799 0.815 0.831 V VIN = 3.3V to 45V 6
FB current IFB -50 0 50 nA VFB = 0.85V 6
Switching frequency fSW 420 470 520 kHz RFREQ = 62kΩ 6
Switching frequency fSW 820 1000 1180 kHz RFREQ = 26.1kΩ 6
SYNCIN clock range fSYNC 350 1000 kHz External clock 6
SYNCO high voltage VSYNCO_HIGH 3.3 4.5 V ISYNCO = -1mA 6
High-side current limit ILIMIT 6.4 8 9.6 A Duty cycle = 30% 6
Low-side valley current limit ILIMIT_VALLEY 4.8 6 7.2 A 6
Zero-current detection (ZCD) threshold IZCD -0.15 0.1 0.35 A AAM 7
Low-side reverse current limit ILIMIT_REVERSE 2 4.5 7 A FCCM 7
Switch leakage current ISW_LKG 0.01 1 µA 7
HS-FET on resistance RON_HS 48 80 mΩ VBST - VSW = 5V 7
LS-FET on resistance RON_LS 20 40 mΩ VCC = 5V 7
Soft-start current ISS 4 6 8 µA VSS = 0V 7
EN rising threshold VEN_RISING 0.8 1 1.2 V 7
EN falling threshold VEN_FALLING 0.65 0.85 1.05 V 7
PG rising threshold (VFB/VREF) PGRISING 88.5 93 97.5 % VFB rising 7
PG rising threshold (VFB/VREF) PGRISING 101.5 106 110.5 % VFB falling 7
PG falling threshold (VFB/VREF) PGFALLING 86.5 91 95.5 % VFB falling 7
PG falling threshold (VFB/VREF) PGFALLING 103 107.5 112 % VFB rising 7
PG output voltage low VPG_LOW 0.1 0.3 V ISINK = 1mA 7
VIN and EN voltage VIN, EN -0.3 50 V 5
All other pins voltage -0.3 5.5 V 5
Continuous power dissipation (QFN-20 4mmx4mm) 5.4 W TA = 25°C 5
Operating junction temperature 150 °C 5
Lead temperature 260 °C 5
Storage temperature -65 150 °C 5
ESD human body model (HBM) -2 2 kV 5
ESD charged device model (CDM) -750 750 V 5
Supply voltage VIN VIN 3.3 45 V 5
Output voltage VOUT VOUT 0.815 V Maximum printed as 0.95 x VIN 5
Operating junction temperature (TJ) TJ -40 125 °C 5
Thermal resistance junction-to-case θJC 9 °C/W JESD51-7, 4-layer PCB 5
VCC current limit ILIMIT_VCC 100 mA VCC = 4V 6
VIN UVLO hysteresis INUVLO_HYS 280 mV 6
VIN quiescent current (switching), AAM IQ_ACTIVE 20 μA MODE = GND (AAM), switching, no load, RFB_UP = 1MΩ, RFB_DOWN = 324kΩ 6
VIN quiescent current (switching), FCCM IQ_ACTIVE 40 mA MODE = high (FCCM), switching, fSW = 2MHz, no load 6
VIN quiescent current (switching), FCCM IQ_ACTIVE 9.5 mA MODE = high (FCCM), switching, fSW = 470kHz, no load 6
Minimum on time tON_MIN 100 ns 6
Minimum off time tOFF_MIN 80 ns 6
SYNCIN voltage rising threshold VSYNC_RISING 1.8 V 6
SYNCIN voltage falling threshold VSYNC_FALLING 0.4 V 6
SYNCO low voltage VSYNCO_LOW 0.4 V ISYNCO = 1mA 6
SYNCO phase shift 180 deg Tested under SYNCIN 6
EN hysteresis voltage VEN_HYS 190 mV 7
MODE rising threshold VMODE_RISING 1.8 V 7
MODE falling threshold VMODE_FALLING 0.4 V 7
PG rising delay tPG_R_DELAY 35 µs 7
PG falling delay tPG_F_DELAY 35 µs 7
Thermal shutdown TSD 170 °C 7
Thermal shutdown hysteresis TSD_HYS 20 °C 7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper as possible to the VIN and GND pins. 2. Connect a large copper ground plane 30

CAD (KiCad official)

  • Symbol: MP4315GRE-Z
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20(4x4) (KiCad packages3D, STEP)
  • 3D model files: mp4315gre-z-etched.step / mp4315gre-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp4315gre-z.step / mp4315gre-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Monolithic Power Systems datasheet (34 pp, sha256 5ea06c2bcd722c63, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF