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MP3437GJ-Z

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Monolithic Power Systems DC-DC Converters, TSOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MP3437GJ-Z

Monolithic Power Systems · DC-DC Converters · TSOT-23-8

MP3437GJ-Z from Monolithic Power Systems, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BST passive Bootstrap pin; a capacitor between BST and SW powers the synchronous high-side MOSFET (absolute maximum BST is VSW + 4.5V).
2 VOUT power_out Output pin connected to the drain of the high-side MOSFET (HS-FET); it powers VDD when VOUT is above VIN and VIN is below 3.4V (absolute maximum -0.3V to +18V).
3 SW passive Converter switch pin connected to the drain of the low-side MOSFET and the source of the high-side MOSFET; connect the power inductor to SW (absolute maximum -0.3V to +18V, -5V for under 10ns).
4 GND power_in Power ground; the datasheet recommends connecting the analog signal close to this GND pin.
5 FB input Feedback input; connect a resistor divider from the VOUT pin to the FB pin (absolute maximum -0.3V to +4.5V).
6 VDD power_out Internal bias supply that must be decoupled with a 4.7µF ceramic capacitor as close to the pin as possible; the regulator from VIN to VOUT is disabled if the bias voltage exceeds 3.4V, and the maximum external VDD bias is 3.6V.
7 EN input Chip enable control that programs VIN's under-voltage lockout; it must not be floated and must be pulled up or down externally, and connecting it to VIN gives automatic start-up (absolute maximum -0.3V to +18V).
8 VIN power_in Input supply that must be bypassed locally and supplied above 2.7V during start-up to provide enough voltage to VDD (operation range 0.8V to 16V, absolute maximum -0.3V to +18V).

Key specifications

Parameter Value
Manufacturer Monolithic Power Systems
Package TSOT-23-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
SW pin voltage -0.3 18 V 4
SW pin voltage transient -5 22 V <10ns 4
VIN, EN, MODE, VOUT pin voltage -0.3 18 V 4
BST pin voltage -0.3 V max = VSW + 4.5V 4
All other pins voltage -0.3 4.5 V 4
HS-FET body diode inrush current 15 A during input start-up (note 2) 4
Continuous power dissipation TSOT23-8 PD 2.4 W TA = 25°C 4
Junction temperature TJ 150 °C 4
Lead temperature 260 °C 4
Storage temperature -65 150 °C 4
ESD human body model 2000 V HBM 4
ESD charged device model 750 V CDM 4
Start-up input voltage VST 2.7 16 V 4
Operation input voltage VIN 0.8 16 V 4
Startup input voltage with VDD bias VST2 0.95 16 V 4
Maximum external VDD bias voltage VDD 3.6 V 4
Boost output voltage VOUT 16 V minimum is VIN (expression as printed) 4
Operating junction temperature TJ -40 125 °C 4
Start-up input voltage VST 2.7 16 V No VDD bias 5
Start-up input voltage VST 0.95 16 V VDD = 3V 5
Operating input voltage VIN 0.8 16 V 5
Operating VDD voltage VDD 2.3 2.6 V VIN = 2.7V, 0mA 5
VDD under-voltage lockout rising threshold VDDUVLO_R 2.2 2.4 2.6 V VDD rising 5
VDD UVLO falling threshold VDDUVLO_F 2 2.2 2.4 V VDD falling 5
Quiescent current (measured on VIN) IQ 3 6 μA VFB = 1.05V, VIN = 3V, VOUT = 8V, no switching, measured on VIN 5
Quiescent current (measured on VOUT) IQ 380 500 μA VFB = 1.05V, VIN = 3V, VOUT = 8V, no switching, measured on VOUT 5
Quiescent current in pass-through mode IQ 430 550 μA VFB = 1.05V, VIN = 9V, VOUT floating, PSM, pass-through mode, measured on VIN 5
EN turn-on voltage threshold VEN_ON 1.15 1.23 1.31 V VEN rising (switching) 5
EN turn-on hysteresis IEN_HYS 3.5 5 6.5 μA 1.0V < EN < VEN_ON 5
Switching frequency fSW 500 600 700 kHz VIN = 3.3V, VOUT = 8V 5
FB reference voltage VREF 0.99 1 1.01 V TJ = 25°C 5
FB reference voltage VREF 0.985 1 1.015 V TJ = -40°C to +125°C 5
HS-FET zero-current detection (ZCD) -200 0 300 mA PSM, VFB = 1V, L = 1.5μH, VOUT = 8V 5
Switching current limit IPK_LIMT 8.5 9.5 11 A 6
Output over-voltage protection (OVP) threshold 16 16.5 V 6
Operating VDD voltage at 12V input VDD 3.4 V VIN = 12V, 0mA - 10mA 5
Shutdown current ISD 2 μA VEN = 0V, measured on VIN 5
EN high voltage threshold VEN_H 1 V VEN rising (micro-power) 5
EN low voltage threshold VEN_L 0.4 V VEN falling (micro-power) 5
EN input current IEN 0 μA VEN = 0V, 1.5V 5
EN turn-on delay 220 μs EN is on, IC starts switching 5
LS-FET minimum on time tMIN_ON 130 ns 5
LS-FET maximum on time tMAX_ON 7.5 μs 5
FB input current IFB 50 nA VFB = 1.05V 5
Soft-start time tSS 4 ms VFB from 0V to 1V 5
LS-FET switch on resistance RON_L 14 mΩ 6
High-side synchronous switch on resistance RON_H 21 mΩ 6
LS-FET leakage current 0.1 μA VSW = 16V, TJ = 25°C 6
HS-FET leakage current 0.1 μA VOUT = 16V, VSW = 0V, TJ = 25°C 6
Output OVP hysteresis 0.5 V 6
FB OVP threshold 110 % VREF PSM only (note 15) 6
FB OVP hysteresis 3 % VREF PSM only (note 15) 6
Thermal shutdown TSD 150 °C 6
Thermal shutdown hysteresis TSD_HYS 25 °C 6
Thermal resistance junction-to-case θJC 12 °C/W EVL3437-J-00A 4
Thermal resistance junction-to-case θJC 55 °C/W JESD51-7 JEDEC board 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper package, connect the SW pin on the top PCB layer using the copper that is under the IC 22

CAD (KiCad official)

  • Symbol: MP3437GJ-Z
  • Footprint: Package_TO_SOT_SMD:TSOT-23-8
  • 3D model: TSOT-23-8 (KiCad packages3D, STEP)
  • 3D model files: mp3437gj-z-etched.step / mp3437gj-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp3437gj-z.step / mp3437gj-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Monolithic Power Systems datasheet (27 pp, sha256 9dd3a7e86130a89a, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF