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MP2637GR-Z

MPS(芯源) · Battery Management · QFN-24(4x4)

MP2637GR-Z from MPS(芯源), in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGND power_in Power ground pin for the charger power stage, returned to the PGND plane alongside the input, SYS and battery decoupling capacitors.
2 CHG output Charge completion indicator; logic LOW indicates charge mode, and the pin is open-drain during charge complete or suspended.
3 BOOST output Boost-mode indicator; logic LOW indicates boost mode is in operation, and the pin is open-drain during charge mode or sleep mode.
4 CSP input Battery charge current sense positive input.
5 BATT bidirectional Positive battery terminal and battery charge current sense negative input, with a 2.5V to 4.35V battery voltage recommended operating range.
6 AGND power_in Analog ground.
7 OLIM input Programmable boost-mode output current limit; connect an external resistor to GND, which CANNOT be lower than 47.5kΩ.
8 ISET input Programmable charge current pin; connect an external resistor to GND to program the charge current.
9 NTC input Negative temperature coefficient thermistor input for battery temperature monitoring.
10 FB input System voltage feedback input for boost mode, with a 1.2V feedback reference per the electrical characteristics.
11 ACOK output Valid input supply indicator; logic LOW on this pin indicates the presence of a valid power supply.
12 REG input Input voltage feedback for the input voltage regulation loop; connect to the tap of a resistor divider from VIN to GND.
13 TMR passive Oscillator period timer; connect a timing capacitor to GND to set the timer period, or short to GND to disable the timer function.
14 PWIN input Input pin detecting valid input power; a voltage between 0.8V and 1.15V is valid, and pulling this pin to GND turns off the IN-to-SYS pass-through MOSFET.
15 ILIM input Input current set; connect to GND with an external resistor to program the charge-mode input current limit, where RILIM must exceed 16.5kΩ.
16 VCC power_out Internal circuit power supply; bypass to GND with a ceramic capacitor not higher than 100nF, and the pin CANNOT carry an external load higher than 5mA.
17 VB power_in Programmable battery-full voltage; leave floating or connect to logic HIGH for 4.2V, or connect to GND for 4.35V.
18 EN input Charge control input; logic HIGH enables charging and logic LOW disables charging, active only when ACOK is low.
19 MODE input Mode select; logic HIGH selects boost mode and logic LOW selects sleep mode, active only when ACOK is high.
20 VIN power_in Adapter input; place a bypass capacitor close to this pin to prevent large input voltage spikes, with a recommended operating range of 4.5V to 6V.
21 SYS power_out System output; a minimum of 22µF ceramic capacitor must be placed as close as possible to the SYS and PGND pins, with total capacitance not lower than 44µF.
22 SW output Switch output node; it is recommended not to place vias on the SW plane during PCB layout.
23 PGND power_in Power ground.
24 PGND power_in Power ground.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer MPS(芯源)
Package QFN-24(4x4)
Category Power Management (PMIC)
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VIN VIN -0.3 20 V 5
SYS pin voltage SYS -0.3 6.5 V 5
SW pin voltage SW -0.3 6.5 V 5
SW pin transient voltage SW -2 8.5 V Transient, <20ns 5
BATT pin voltage BATT -0.3 6.5 V 5
ACOK, CHG, BOOST pin voltage ACOK, CHG, BOOST -0.3 6.5 V 5
All other pins voltage -0.3 6.5 V 5
Junction temperature 150 °C 5
Storage temperature -65 150 °C 5
Supply voltage VVIN 4.5 6 V 5
Battery voltage VBATT 2.5 4.35 V 5
Operating junction temperature TJ -40 125 °C 5
IN to SYS NMOS ON resistance RIN to SYS 65 mΩ VCC=5V 6
High-side PMOS ON resistance RH_DS 30 mΩ VCC=5V 6
Low-side NMOS ON resistance RL_DS 30 mΩ VCC=5V 6
High-side PMOS peak current limit IPEAK_HS 6.5 A CC Charge Mode/ Boost Mode 6
High-side PMOS peak current limit IPEAK_HS 3.2 A TC Charge Mode 6
Low-side NMOS peak current limit IPEAK_LS 6.3 A 6
Switching frequency fsw 490 600 700 kHz 6
VCC UVLO VCC_UVLO 2 2.2 2.4 V 6
PWIN lower threshold VPWIN_L 0.75 0.8 0.85 V 6
PWIN upper threshold VPWIN_H 1.1 1.15 1.2 V 6
Input quiescent current, charge mode IIN 2.5 mA EN = 5V, Battery Float 6
Input quiescent current, charge mode IIN 1.5 mA EN = 0 6
Input current limit IIN_LIMIT 400 450 500 mA RILIM = 100k 6
Input current limit IIN_LIMIT 720 810 900 mA RILIM = 56k 6
Input current limit IIN_LIMIT 2400 2700 3000 mA RILIM = 16.5k 6
Input over-current threshold IIN(OCP) 4.2 A 6
Terminal battery voltage VBATT_FULL 4.328 4.35 4.372 V Connect VB to GND 6
Terminal battery voltage VBATT_FULL 4.179 4.2 4.221 V Leave VB floating or connect to logic HIGH 6
Recharge threshold VRECH 4.09 4.15 4.21 V Connect VB to GND 6
Recharge threshold VRECH 3.95 4.01 4.07 V Leave VB floating or connect to logic HIGH 6
Battery over voltage threshold 103.3 % As percentage of the VBATT_FULL 6
Constant charge (CC) current ICC 850 1000 1150 mA RS1 = 20mΩ, RISET = 120k 6
Constant charge (CC) current ICC 1725 1987 2250 mA RS1 = 20mΩ, RISET = 60.4k 6
Constant charge (CC) current ICC 2225 2525 2825 mA RS1 = 20mΩ, RISET = 47.5k 6
Trickle charge current ITC 125 250 mA 6
Trickle charge voltage threshold VBATT_TC 3 3.1 3.2 V Connect VB to GND 7
Trickle charge voltage threshold VBATT_TC 2.9 3 3.1 V Leave VB floating or connect to high logic 7
Termination charge current IBF 2.5 10 17.5 % ICC RS1 = 20mΩ, RISET=60.4k 7
Input-voltage-regulation reference VREG 1.18 1.2 1.22 V 7
SYS voltage range 4.2 6 V 7
Feedback voltage 1.18 1.2 1.22 V 7
Feedback input current 200 nA VFB=1V 7
Boost SYS over-voltage protection threshold VSYS(OVP) 5.6 5.75 5.9 V Threshold over VSYS to turn off the converter during boost mode 7
Boost quiescent current 1.4 mA ISYS = 0, MODE = 5V 7
Programmable boost output current limit accuracy IOLIM 1.875 2.083 2.29 A RS1 = 20mΩ, ROLIM = 57.6k 7
Programmable boost output current limit accuracy IOLIM 2.1 A RS1 = 20mΩ, ROLIM = 51k 7
Weak-battery threshold VBATT(LOW) 2.5 V During boosting 7
Weak-battery threshold VBATT(LOW) 2.9 3.05 V Before Boost starts 7
Battery leakage current ILEAKAGE 15 30 μA VBATT = 4.2V, SYS Float, VIN = 0V, MODE = 0V 7
ACOK, CHG, BOOST pin output low voltage 400 mV Sinking 1.5mA 7
ACOK, CHG, BOOST pin leakage current 1 μA Connected to 5V 7
NTC low temp rising threshold VTL/VSYS 65.6 66.6 67.6 % VSYS RNTC=NCP18XH103(0ºC) 8
NTC high temp rising threshold VTH/VSYS 34 35 36 % VSYS RNTC=NCP18XH103(50ºC) 8
Charging current foldback threshold 120 °C Charge Mode 8
Thermal shutdown threshold 150 °C 8
Thermal resistance junction-to-ambient θJA 42 °C/W QFN-24 (4mm×4mm); Measured on JESD51-7, 4-layer PCB 5
Thermal resistance junction-to-case θJC 9 °C/W QFN-24 (4mm×4mm); Measured on JESD51-7, 4-layer PCB 5

CAD (KiCad official)

  • Symbol: MP2637GR-Z
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: mp2637gr-z-etched.step / mp2637gr-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp2637gr-z.step / mp2637gr-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MPS(芯源) datasheet (37 pp, sha256 a32255bb902badab, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF