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MP2617HGL-Z

Public Made by Adom

by adom

MPS Others, QFN-20(3x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MP2617HGL-Z

MPS · Others · QFN-20(3x4)

MP2617HGL-Z from MPS, in a QFN-20(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BST passive Bootstrap pin where a capacitor is connected between SW and BST to form a floating supply that drives the power switch gate above the supply voltage.
2 SW power_out Switch output; add an external 30V/1A Schottky diode from SW to GND when VIN is 12V or higher and output power (system load plus battery charging) exceeds 10W.
3 IN power_in Power input of the IC from adapter or USB, recommended 4.0V to 14V.
4 SW power_out Switch output; add an external 30V/1A Schottky diode from SW to GND when VIN is 12V or higher and output power (system load plus battery charging) exceeds 10W.
5 PGND power_in Power ground.
6 EN input Active-low function logic control of the IC; drive low to enable the part and high to disable it.
7 M0 input Mode select input that sets the input current limit mode in combination with M1.
8 M1 input Mode select input that sets the input current limit mode in combination with M0.
9 CHGOK output Open-drain output pulled low during charging and pulled high through an external resistor to VCC to indicate charge complete.
10 ACOK output Open-drain output pulled low to indicate a valid input power supply and pulled high through an external resistor to VCC for an invalid or removed input.
11 AGND power_in Analog ground.
12 SYSFB input SYS voltage program; connect a resistor divider from SYSFB to SYS and AGND to program the system output voltage, or leave floating to disable the function.
13 SYS power_out DC/DC regulator output to power the system load and charge the battery (absolute maximum -0.3V to +6V).
14 BATT bidirectional Positive battery terminal (absolute maximum -0.3V to +6V).
15 ISET input Charge current program; a resistor from ISET to AGND programs the CC charge current, and floating ISET disables the charge function.
16 NTC input Thermistor input; connect a resistor from NTC to VCC and the battery-pack thermistor from NTC to ground.
17 ILIM input Input current limit program; a resistor from ILIM to AGND programs the input current limit with the adapter input.
18 TMR input Timer out period set; connect a 0603 ceramic capacitor from TMR to GND to set the period, or connect TMR to AGND to disable the internal timer.
19 VLIM input Input voltage limit program.
20 VCC power_out Supply voltage of the IC.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer MPS
Package QFN-20(3x4)
Category Others
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
IN operating range VIN 4 14 V 6
IN UVLO threshold rising 3.65 3.8 3.95 V Rising 6
IN UVLO threshold falling 3.35 3.5 3.65 V Falling 6
IN vs. BATT threshold rising 240 280 320 mV Rising 6
IN vs. BATT threshold falling 40 70 120 mV Falling 6
BST voltage threshold rising VBST - VSW 2.55 2.9 3.25 V Rising 6
Switching frequency 1.4 1.6 1.8 MHz 6
Input current limit USB2.0 mode IIN 400 450 500 mA USB2.0 mode 6
Input current limit USB3.0 mode IIN 750 825 900 mA USB3.0 mode 6
Input current limit default mode IIN 1840 2000 2160 mA Default mode 6
Input current limit programmable mode IIN 1840 2000 2160 mA Programmable mode, RILIM = 23kΩ 6
Input current limit reference voltage VILIM 1.1 1.14 1.18 V 6
High-side NMOS on resistance RH_DS(ON) 120 130 mΩ Include the block MOSFET 6
Low-side NMOS on resistance RL_DS(ON) 80 100 mΩ 6
High-side NMOS peak current limit 3.8 4.8 5.8 A 6
Input voltage clamp threshold VVLIM 1.49 1.52 1.55 V Voltage on VLIM 6
Input quiescent current USB2.0 IIN 2.4 5 mA Charger enabled, USB2.0 mode 6
Input quiescent current USB3.0 IIN 2.8 5 mA Charger enabled, USB3.0 mode 6
Input quiescent current programmable IIN 3.8 5 mA Charger enable, programmable mode 6
Input quiescent current default IIN 3.8 5 mA Charger enabled, default mode 6
Input quiescent current disabled IIN 3 5 µA Disabled, EN = 0V 6
SYS to IN reverse current blocking 0.01 0.2 µA SYS = SW = 4.5V, VIN = 0V, monitor VIN leakage 6
Minimum SYS regulation voltage VSYS 3.45 3.6 3.75 V SYS voltage at VBATT ≤ 3.4V, SYSFB float 6
SYS regulation voltage VSYS 3.5 4.5 V 3.4V < VBATT ≤ 4.2V, SYSFB float, BATT float; typ VBATT + 0.2V 6
SYS regulation voltage programmed by SYSFB VSYS 4.08 4.4 V Programmed by SYSFB 6
SYS reference voltage VSYS_REF 1.135 1.152 1.17 V 6
BATT to SYS resistance 40 50 mΩ VIN = 0V, ISYS = 200mA, VBATT = 4.2V 6
BATT to SYS current limit 5 6.2 7.4 A VSYS > VBATT - 800mV, VBATT = 4.2V 6
Terminal battery voltage VBATT 4.179 4.2 4.221 V VBATT > VRECH, ICHG ≤ IBF, SYSFB float 7
Recharge threshold SYSFB float VRECH 3.9 4 4.1 V SYSFB float 7
Recharge threshold SYSFB programmed VRECH 3.85 3.95 4.05 V SYSFB programmed 7
Trickle charge threshold 2.9 3 3.1 V 7
Termination charger current IBF 5 10 15 % ICC 7
IBF maximum limit 150 200 mA 7
CC mode charge current RISET=760Ω ICC 2.475 2.75 3.025 A RISET = 760Ω 7
CC mode charge current RISET=1.53kΩ ICC 1.26 1.4 1.54 A RISET = 1.53kΩ 7
CC mode charge current RISET=4.6kΩ ICC 0.405 0.45 0.495 A RISET = 4.6kΩ 7
ISET reference voltage 1.1 1.15 1.2 V 7
Battery UVLO rising 2.4 2.6 2.8 V Rising 7
Battery UVLO falling 2.2 2.4 2.6 V Falling 7
BATT leakage current IBATT 20 30 µA VBATT = 4.2V, SYS float, VIN = PGND 7
ACOK, CHGOK output low voltage 270 350 mV Sinking 5mA 7
ACOK, CHGOK leakage current 0.1 0.5 μA Connected to 3.3V 7
NTC low temp rising threshold VTHL 63 65 67 %VCC RNTC = NCP18XH103F, 0°C 7
NTC high temp falling threshold VTHH 32 33.5 35 %VCC RNTC = NCP18XH103F, 50°C 7
VCC UVLO rising 3.15 3.35 3.55 V Rising 8
VCC UVLO falling 2.8 3 3.2 V Falling 8
VCC output voltage 4.3 4.5 4.6 V 0mA < IVCC < 25mA, VIN = 6V 8
EN input low voltage 0.4 V 8
EN input high voltage 1.5 V 8
EN input current high 4 8 μA EN = 4V 8
EN input current low -0.5 -0.1 μA EN = 0V 8
M0, M1 logic high 1.5 V 8
M0, M1 logic low 0.4 V 8
Supply voltage (IN) VIN 4 14 V 5
Operating junction temperature TJ -40 125 °C 5
IN, SW voltage -0.3 20 V 5
BATT, SYS voltage -0.3 6 V 5
BST voltage -0.3 26 V 5
All other pins voltage -0.3 6 V 5
Continuous power dissipation 2.6 W TA = +25°C, QFN-20 (3mmx4mm) 5
Junction temperature TJ 150 °C 5
Storage temperature -65 150 °C 5
Thermal resistance junction-ambient θJA 48 °C/W QFN-20 (3mmx4mm), JESD51-7 4-layer PCB 5
Thermal resistance junction-case θJC 11 °C/W QFN-20 (3mmx4mm), JESD51-7 4-layer PCB 5

CAD (KiCad official)

  • Symbol: MP2617HGL-Z
  • Footprint: Package_DFN_QFN:QFN-20-1EP_3x4mm_P0.5mm_EP1.65x2.65mm
  • 3D model: QFN-20(3x4) (KiCad packages3D, STEP)
  • 3D model files: mp2617hgl-z-etched.step / mp2617hgl-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp2617hgl-z.step / mp2617hgl-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MPS datasheet (33 pp, sha256 bdec7c58d9a766ff, retrieved 2026-10-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF