component
MP20075DH-LF-Z
Public Made by Adomby adom
Monolithic Power Systems Power Management - Specialized, MSOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MP20075DH-LF-Z
Monolithic Power Systems · Power Management - Specialized · MSOP-8-EP
MP20075DH-LF-Z from Monolithic Power Systems, in a MSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DDQ | power_in | Power input for the VTT regulator, normally connected to the DDR2/3/3L/4 VDDQ rail and bypassed with a 10μF ceramic capacitor; absolute maximum supply voltage VDDQ is -0.3V to 3.6V. |
| 2 | VTT | power_out | Output of the VTT LDO, a precision VREF/2 voltage that tracks VREF, which sources or sinks up to 3A and is recommended to be bypassed with 2x10μF ceramic capacitors. |
| 3 | GND | power_in | Ground pin, which must be connected to the same ground plane as the exposed pad. |
| 4 | VTTSEN | input | Kelvin-sensed feedback input that should be connected to the VTT regulation point (usually the VTT local bypass capacitor) through a direct sense trace. |
| 5 | VDRV | power_in | Chip bias voltage that should be connected to a 3.3V supply within the recommended 3.0V to 3.5V range and bypassed with a 4.7μF capacitor. |
| 6 | REF | input | LDO signal input used to generate the VDDQ/2 reference, to be bypassed with a 0.1μF capacitor. |
| 7 | EN | input | VTT regulator enable input where EN high enables the MP20075, with EN_H threshold of 1.4V and EN_L threshold of 0.5V, and the datasheet calls for a 100k pull-up resistor. |
| 8 | VTTREF | output | Precision buffered VREF/2 output that tracks VREF with a drive capability of up to 10mA for the DDR memory input comparators. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | MSOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDRV Operating Voltage | VDRV | 3 | 3.3 | 3.5 | V | ITT=3A | 3 |
| VDRV Shut down current | IDRV_SD | 0.2 | 1 | μA | VDRV =3.3 V, VDDQ=0V | 3 | |
| VDRV Operation Current | IDRV | 1.3 | 3 | mA | VEN_H, VTT=0.75V | 3 | |
| VDDQ UVLO Upper Threshold | VDDQUV+ | 0.9 | 1 | V | Rising Edge; hysteresis = 55mV | 3 | |
| VTT with Respect to 1/2VREF (sink) | dVTT0 | -30 | 30 | mV | VREF = 1.8V, IVTT = 0 to 3A (Sink Current) | 3 | |
| VTT with Respect to 1/2VREF (source) | dVTT0 | -30 | 30 | mV | VREF = 1.8V, IVTT = 0 to 3A (Source Current) | 3 | |
| VTTREF Accuracy Referred to 1/2VREF | dVTTR | -18 | 18 | mV | VREF = 1.8 V, IVTTR = 0mA to 10mA | 3 | |
| VTTREF Accuracy Referred to 1/2VREF | dVTTR | -15 | 15 | mV | VREF = 1.5 V, IVTTR = 0mA to 10mA | 3 | |
| Source Current Limit | ILIMVTsrc | 4 | A | 3 | |||
| Sink Current Limit | ILIMVTsnk | 4 | A | 3 | |||
| Soft-Start Source Current Limit | ILIMVTSS | 1 | A | 3 | |||
| Maximum Soft-Start Time | tssvttmax | 9 | μs | VREF=1.8, VDRV=3.3V | 3 | ||
| Maximum Soft-Start Time | tssvttmax | 7 | μs | VREF=1.5V, VDRV=3.3V | 3 | ||
| VTTREF Source Current | IVTTR | 10 | mA | VREF = 1.8 V or 1.5 V | 3 | ||
| EN Pin Threshold High | EN_H | 1.4 | V | 3 | |||
| EN Pin Threshold Low | EN_L | 0.5 | V | 3 | |||
| EN Pin Input Current | IIN_EN | 1 | μA | EN = 3.3 V | 3 | ||
| Thermal Trip Point | TSD | 150 | °C | 3 | |||
| Thermal Shutdown Hysteresis | TSDHYS | 25 | °C | 3 | |||
| Supply Voltage VDDQ | VDDQ | -0.3 | 3.6 | V | 2 | ||
| Drive Voltage VDRV | VDRV | -0.3 | 6 | V | 2 | ||
| All Other Pins | -0.3 | 6 | V | 2 | |||
| Continuous Power Dissipation | 1.56 | W | TA = +25°C | 2 | |||
| Junction Temperature | 150 | °C | 2 | ||||
| Storage Temperature | -50 | 150 | °C | 2 | |||
| Drive Voltage VDRV (recommended) | VDRV | 3 | 3.5 | V | 2 | ||
| Operating Junction Temperature | TJ | -40 | 125 | °C | 2 | ||
| Thermal Resistance Junction-to-Ambient (MSOP8E) | θJA | 50 | °C/W | Measured on JESD51-7 4-layer board | 2 | ||
| Thermal Resistance Junction-to-Case (MSOP8E) | θJC | 12 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
MP20075DH-LF-Z - Footprint:
Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.5x1.8mm - 3D model: MSOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
mp20075dh-lf-z-etched.step/mp20075dh-lf-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp20075dh-lf-z.step/mp20075dh-lf-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems datasheet (11 pp, sha256
1ffd1742b5c1a12a, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MP20075DH-LF-Z
**Monolithic Power Systems** · Power Management - Specialized · MSOP-8-EP
MP20075DH-LF-Z from Monolithic Power Systems, in a MSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DDQ | power_in | Power input for the VTT regulator, normally connected to the DDR2/3/3L/4 VDDQ rail and bypassed with a 10μF ceramic capacitor; absolute maximum supply voltage VDDQ is -0.3V to 3.6V. |
| 2 | VTT | power_out | Output of the VTT LDO, a precision VREF/2 voltage that tracks VREF, which sources or sinks up to 3A and is recommended to be bypassed with 2x10μF ceramic capacitors. |
| 3 | GND | power_in | Ground pin, which must be connected to the same ground plane as the exposed pad. |
| 4 | VTTSEN | input | Kelvin-sensed feedback input that should be connected to the VTT regulation point (usually the VTT local bypass capacitor) through a direct sense trace. |
| 5 | VDRV | power_in | Chip bias voltage that should be connected to a 3.3V supply within the recommended 3.0V to 3.5V range and bypassed with a 4.7μF capacitor. |
| 6 | REF | input | LDO signal input used to generate the VDDQ/2 reference, to be bypassed with a 0.1μF capacitor. |
| 7 | EN | input | VTT regulator enable input where EN high enables the MP20075, with EN_H threshold of 1.4V and EN_L threshold of 0.5V, and the datasheet calls for a 100k pull-up resistor. |
| 8 | VTTREF | output | Precision buffered VREF/2 output that tracks VREF with a drive capability of up to 10mA for the DDR memory input comparators. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | MSOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDRV Operating Voltage | VDRV | 3 | 3.3 | 3.5 | V | ITT=3A | 3 |
| VDRV Shut down current | IDRV_SD | | 0.2 | 1 | μA | VDRV =3.3 V, VDDQ=0V | 3 |
| VDRV Operation Current | IDRV | | 1.3 | 3 | mA | VEN_H, VTT=0.75V | 3 |
| VDDQ UVLO Upper Threshold | VDDQUV+ | 0.9 | | 1 | V | Rising Edge; hysteresis = 55mV | 3 |
| VTT with Respect to 1/2VREF (sink) | dVTT0 | -30 | | 30 | mV | VREF = 1.8V, IVTT = 0 to 3A (Sink Current) | 3 |
| VTT with Respect to 1/2VREF (source) | dVTT0 | -30 | | 30 | mV | VREF = 1.8V, IVTT = 0 to 3A (Source Current) | 3 |
| VTTREF Accuracy Referred to 1/2VREF | dVTTR | -18 | | 18 | mV | VREF = 1.8 V, IVTTR = 0mA to 10mA | 3 |
| VTTREF Accuracy Referred to 1/2VREF | dVTTR | -15 | | 15 | mV | VREF = 1.5 V, IVTTR = 0mA to 10mA | 3 |
| Source Current Limit | ILIMVTsrc | | 4 | | A | | 3 |
| Sink Current Limit | ILIMVTsnk | | 4 | | A | | 3 |
| Soft-Start Source Current Limit | ILIMVTSS | | 1 | | A | | 3 |
| Maximum Soft-Start Time | tssvttmax | | 9 | | μs | VREF=1.8, VDRV=3.3V | 3 |
| Maximum Soft-Start Time | tssvttmax | | 7 | | μs | VREF=1.5V, VDRV=3.3V | 3 |
| VTTREF Source Current | IVTTR | | 10 | | mA | VREF = 1.8 V or 1.5 V | 3 |
| EN Pin Threshold High | EN_H | | 1.4 | | V | | 3 |
| EN Pin Threshold Low | EN_L | | 0.5 | | V | | 3 |
| EN Pin Input Current | IIN_EN | | 1 | | μA | EN = 3.3 V | 3 |
| Thermal Trip Point | TSD | | 150 | | °C | | 3 |
| Thermal Shutdown Hysteresis | TSDHYS | | 25 | | °C | | 3 |
| Supply Voltage VDDQ | VDDQ | -0.3 | | 3.6 | V | | 2 |
| Drive Voltage VDRV | VDRV | -0.3 | | 6 | V | | 2 |
| All Other Pins | | -0.3 | | 6 | V | | 2 |
| Continuous Power Dissipation | | | | 1.56 | W | TA = +25°C | 2 |
| Junction Temperature | | | | 150 | °C | | 2 |
| Storage Temperature | | -50 | | 150 | °C | | 2 |
| Drive Voltage VDRV (recommended) | VDRV | 3 | | 3.5 | V | | 2 |
| Operating Junction Temperature | TJ | -40 | | 125 | °C | | 2 |
| Thermal Resistance Junction-to-Ambient (MSOP8E) | θJA | | 50 | | °C/W | Measured on JESD51-7 4-layer board | 2 |
| Thermal Resistance Junction-to-Case (MSOP8E) | θJC | | 12 | | °C/W | | 2 |
## CAD (KiCad official)
- Symbol: `MP20075DH-LF-Z`
- Footprint: `Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.5x1.8mm`
- 3D model: MSOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `mp20075dh-lf-z-etched.step` / `mp20075dh-lf-z-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mp20075dh-lf-z.step` / `mp20075dh-lf-z.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Monolithic Power Systems datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590906849816358912) (11 pp, sha256 `1ffd1742b5c1a12a`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mp20075dh-lf-z-datasheet.pdf)