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MP20051DN-LF-Z

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Monolithic Power Systems Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MP20051DN-LF-Z

Monolithic Power Systems · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP

MP20051DN-LF-Z from Monolithic Power Systems, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT power_out Regulator output that must be bypassed with a standard 4.7μF ceramic capacitor to GND, with pins 1, 2, 7 and 8 connected externally as stated by the datasheet.
2 VOUT power_out Regulator output that must be bypassed with a standard 4.7μF ceramic capacitor to GND, with all output pins connected together externally.
3 FB input Feedback input connected to the center point of the external resistor divider, with a feedback threshold voltage of 0.8V.
4 GND power_in Ground pin; the exposed pad on the package backside must also be connected to the GND plane for optimal thermal performance.
5 EN input Regulator enable input: drive above 1.5V to turn the device on and below 0.4V to turn it off, and do not float this pin.
6 NC unconnected No connection; this pin must be left open.
7 VIN power_in Regulator input with a supply voltage range of 2.5V to 5.5V, bypassed with a 2.2μF capacitor and externally connected to pin 8 for proper operation.
8 VIN power_in Regulator input with a supply voltage range of 2.5V to 5.5V, bypassed with a 2.2μF capacitor and externally connected to pin 7 for proper operation.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Monolithic Power Systems
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Input Voltage VIN 2.5 5.5 V 3
Enable Input Voltage VEN 0 5.5 V 3
Operating Junction Temperature TJ -40 125 °C 3
VIN, EN, FB to GND -0.3 6 V 3
OUT to GND -0.5 V upper limit VIN + 0.5V 3
Continuous Power Dissipation SOIC8E PD 2 W TA=25°C 3
Junction Temperature 150 °C 3
Storage Temperature Range -65 150 °C 3
Lead Temperature (Soldering) 260 °C 10sec 3
ESD HBM (Human Body Model) 2 kV 3
ESD MM (Machine Model) 200 V 3
Thermal Resistance Junction to Ambient SOIC8E θJA 50 °C/W JESD51-7, 4-layer PCB 3
Thermal Resistance Junction to Case SOIC8E θJC 10 °C/W 3
Input Under Voltage Lockout UVLO 1.95 2.25 V VIN rising 4
FB Voltage VFB 0.784 0.8 0.816 V VOUT=0.8V, IOUT=1mA 4
Output Voltage Accuracy -2 2 % IOUT=1mA, TA=25°C 4
Output Voltage Accuracy -3 3 % IOUT=1mA, -40≤TA≤85°C 4
In-Regulation Current Limit 1.4 2.2 3 A VOUT=2.5V, VOUT within 4% of normal output voltage, VIN=5.5V 4
Dropout Voltage 140 280 mV IOUT=1A, VOUT=2.5V 4
Dropout Voltage 105 210 mV IOUT=750mA, VOUT=2.5V 4
Dropout Voltage 70 140 mV IOUT=500mA, VOUT=2.5V 4
Line Regulation -0.15 0.15 %/V VOUT=2.5V, VIN from VOUT+0.5V to 5.5V, IOUT=100mA 4
Maximum Output Current 1 A Continuous, VIN≥2.5V, VOUT=2.5V 4
Short-Circuit Current Limit 1.6 A VOUT=0, VIN≥2.5V 4
Load Regulation 0.3 % IOUT from 100mA to 1A, VOUT=2.5V 4
EN Logic High Threshold VEN 1.5 V EN Logic High 4
EN Logic Low Threshold VEN 0.4 V EN Logic Low 4
Ground Current 110 μA IOUT=0.1mA, VOUT=2.5V 4
Ground Current 600 μA IOUT=1A, VOUT=2.5V 4
Output Voltage Noise 13 μVRMS VOUT=1.1V, IOUT=100mA, f 10Hz to 100kHz 4
Output Voltage Noise 35 μVRMS VOUT=3.3V, IOUT=100mA, f 10Hz to 100kHz 4
Output Voltage Noise 55 μVRMS VOUT=5V, IOUT=100mA, f 10Hz to 100kHz 4
PSRR 65 dB VIN = 2.5V, VOUT = 1.1V, IOUT = 1A, f=100Hz 4
PSRR 63 dB VIN = 2.5V, VOUT = 1.1V, IOUT = 1A, f=1kHz 4
PSRR 33 dB VIN = 2.5V, VOUT = 1.1V, IOUT = 1A, f=1MHz 4
Shutdown Supply Current 0.2 μA VIN=+5.5V 4
EN Pin Current, Enabled 0.2 μA VIN=VEN=+5.5V 4
Feedback Pin Current 0.02 μA VIN=+5.5V, VFB=6V 4
Hysteresis of UVLO 160 mV 4
Startup Time 45 μs VOUT(NOM)=2.5V, COUT=4.7μF, VOUT=0% to 90%VOUT(NOM) 4
Thermal Shutdown Temperature 150 °C 4

CAD (KiCad official)

  • Symbol: MP20051DN-LF-Z
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: mp20051dn-lf-z-etched.step / mp20051dn-lf-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp20051dn-lf-z.step / mp20051dn-lf-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Monolithic Power Systems datasheet (13 pp, sha256 082992307ade7d90, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF