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MP1923GS-Z

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by adom

Monolithic Power Systems Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MP1923GS-Z

Monolithic Power Systems · Gate Drivers · SOIC-8

MP1923GS-Z from Monolithic Power Systems, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Supply voltage for the internal circuitry (recommended 5V to 17V, absolute max 18V); connect a decoupling capacitor between VDD and ground.
2 BST power_in Bootstrap positive supply for the floating high-side MOSFET driver (BST to SW max 18V, BST up to 120V); connect a bypass capacitor between BST and SW.
3 DRVH output Floating HS-FET driver output, ranging from VSW - 0.3V to VBST + 0.3V.
4 SW passive Switching node, the high-side driver return, rated -5V to +120V (recommended -1V to +100V).
5 INH input TTL-compatible control signal input for the floating HS-FET driver, with a 155kΩ internal pull-down.
6 INL input TTL-compatible control signal input for the LS-FET driver, with a 155kΩ internal pull-down.
7 VSS power_in Chip ground.
8 DRVL output LS-FET driver output, ranging from -0.3V to VDD + 0.3V.

Key specifications

Parameter Value
Manufacturer Monolithic Power Systems
Package SOIC-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD quiescent current IDD_Q 130 300 µA VINL = VINH = 0V 5
VDD operating current IDD_OP 2.6 6 mA fSW = 500kHz, CLOAD = 0nF 5
Floating driver quiescent current IBST_Q 60 150 µA VINL = VINH = 0V 5
Floating driver operating current IBST_OP 2.6 6 mA fsw = 500kHz, CLOAD = 0nF 5
BST to VSS quiescent current IBST-SS_Q 0.05 1 µA VBST = VSW = 115V 5
BST to VSS operating current IBST-SS_OP 2.3 5.5 mA fSW = 500kHz, CLOAD = 0nF 5
Leakage current ILKG 0.05 1 µA VBST = VSW = 100V 5
INL and INH high voltage 2 2.4 V 5
INL and INH low voltage 1.2 0.8 V 5
VDD rising threshold VDD_RISING 4.6 5 5.4 V 5
VDD falling threshold VDD_FALLING 4.1 4.5 4.9 V 5
(BST - SW) rising threshold VBST_RISING 1.6 3.7 4.9 V 5
(BST - SW) falling threshold VBST_FALLING 1.4 3.2 4.6 V 5
Bootstrap diode VF at 100µA VF1 0.5 0.9 V 5
Bootstrap diode VF at 100mA VF2 1 1.2 V 5
Bootstrap diode dynamic R RD 3.1 6.5 Ω IVDD-BST = 100mA and 80mA 5
LS low-level output voltage VOLL 0.02 0.07 0.2 V IOUT = 100mA 5
LS high-level output voltage to rail VOHL 0.02 0.07 0.3 V IOUT = -100mA 5
HS low level output voltage VOLH 0.02 0.07 0.2 V IOUT = 100mA 5
HS high level output voltage to rail VOHH 0.02 0.07 0.3 V IOUT = -100mA 5
LS turn-off propagation delay tDLFF 5 20 50 ns CLOAD = 0nF, INL falling to DRVL falling 5
LS turn-on propagation delay tDLRR 5 20 50 ns CLOAD = 0nF, INL rising to DRVL rising 5
DRVL rise time tRISE_LS 0.2 0.6 µs CLOAD = 0.1μF, from 3V to 9V 5
DRVL fall time tFALL_LS 0.15 0.4 µs CLOAD = 0.1μF, from 9V to 3V 6
HS turn-off propagation delay tDHFF 5 20 50 ns CLOAD = 0nF, INH falling to DRVH falling 6
HS turn-on propagation delay tDHRR 5 20 50 ns CLOAD = 0nF, INH rising to DRVH rising 6
DRVH rise time tRISE_HS 0.2 0.6 µs CLOAD = 0.1μF, (3V to 9V) 6
DRVH fall time tFALL_HS 0.15 0.4 µs CLOAD = 0.1μF, (9V to 3V) 6
HS turn-off to LS turn-on matching tMON 1 5 ns Guaranteed by design 6
LS turn-off to HS turn-on matching tMOFF 1 5 ns Guaranteed by design 6
Supply voltage VDD -0.3 18 V 4
SW voltage VSW -5 120 V 4
SW voltage (<2µs) VSW -18 120 V <2µs 4
BST voltage VBST -0.3 120 V 4
BST to SW -0.3 18 V 4
DRVL voltage VDRVL -0.3 V max is VDD + 0.3V 4
All other pins to VSS -0.3 10 V 4
Continuous power dissipation SOIC-8 PD 1.3 W SOIC-8 4
Junction temperature TJ 150 °C 4
Storage temperature -65 150 °C 4
ESD HBM -2000 2000 V Human body model 4
ESD CDM -500 500 V Charged device model 4
Supply voltage (operating) VDD 5 17 V 4
SW voltage (operating) VSW -1 100 V 4
SW slew rate 50 V/ns <50V/ns 4
Operating junction temperature TJ -40 125 °C 4
Input voltage hysteresis 600 mV 5
INL internal pull-down resistance RINL 155 kΩ 5
INH internal pull-down resistance RINH 155 kΩ 5
LS source current IOHL 7 A VDRVL = 0V, VDD = 12V 5
LS sink current IOLL 8 A VDRVL = VDD = 12V 5
Minimum input pulse width tPW 50 ns Guaranteed by design 6
Thermal shutdown 165 °C 6
Thermal shutdown hysteresis 25 °C 6

CAD (KiCad official)

  • Symbol: MP1923GS-Z
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: mp1923gs-z-etched.step / mp1923gs-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp1923gs-z.step / mp1923gs-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Monolithic Power Systems datasheet (21 pp, sha256 15d8d0c2660a1db5, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF