component
MP1530DM-LF-Z
Public Made by Adomby adom
Monolithic Power Systems DC-DC Converters, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MP1530DM-LF-Z
Monolithic Power Systems · DC-DC Converters · TSSOP-16
MP1530DM-LF-Z from Monolithic Power Systems, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RDY | output | Regulators-not-ready flag that stays high during startup and on a fault, is pulled low once all FB voltages exceed 80% of threshold, and shuts the chip down if a fault persists beyond approximately 6ms (CT = 10nF). |
| 2 | FB1 | input | Step-up converter feedback input, the inverting input of the internal error amplifier, with a regulation voltage of 1.22V to 1.28V. |
| 3 | COMP | output | Step-up converter error-amplifier output, compensated with a series RC network, with a maximum output current of ±100µA. |
| 4 | IN | power_in | Internal power input supplying the device over a 2.7V to 5.5V range, to be bypassed to PGND with a 10µF or greater capacitor. |
| 5 | GND | power_in | Signal ground, which must be connected to PGND as close to the device as possible. |
| 6 | REF | output | 1.25V reference output (1.22V to 1.28V at IREF = 50µA), to be bypassed to GND with a 0.1µF or greater capacitor and used as the top of the negative regulator feedback string. |
| 7 | FB2 | input | Negative linear regulator feedback input with a regulation threshold of GND (±25mV), with the feedback string connected between GL and REF. |
| 8 | FB3 | input | Positive linear regulator feedback input with a 1.25V regulation threshold (1.22V to 1.28V), with the feedback string connected between GH and GND. |
| 9 | EN | input | On/off control input that turns the device on when driven high (VEN HIGH 1.6V minimum) and off when driven low (VEN LOW 0.3V maximum), with EN tied to IN for automatic startup. |
| 10 | GL | power_out | Negative linear regulator output supplying up to 20mA, to be bypassed to GND with a 1µF or greater low-ESR ceramic capacitor. |
| 11 | IN2 | power_in | Negative linear regulator input driven by an inverting charge pump from SW, which can go as low as -20V. |
| 12 | GH | power_out | Positive linear regulator output supplying up to 20mA, to be bypassed to GND with a 1µF or greater low-ESR ceramic capacitor. |
| 13 | IN3 | power_in | Positive linear regulator input driven by a doubling, tripling or quadrupling charge pump from SW, which can go as high as 38V. |
| 14 | PGND | power_in | Power ground and source of the internal 250mΩ N-channel switch, to be connected to GND as close to the device as possible. |
| 15 | SW | output | Step-up converter switch node, the drain of the internal 250mΩ N-channel MOSFET, with an absolute maximum rating of -0.3V to +25V. |
| 16 | CT | passive | Timing capacitor pin connected to GND that sets the soft-start and power-on sequencing delays, with 10nF giving a 6ms soft-start period. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | TSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.7 | 5.5 | V | 3 | ||
| IN Undervoltage Lockout Threshold | VUVLO | 2.25 | 2.65 | V | IN Rising | 3 | |
| EN Input High Voltage | VEN HIGH | 1.6 | V | EN Rising | 3 | ||
| EN Input Low Voltage | 0.3 | V | 3 | ||||
| COMP Maximum Output Current | -100 | 100 | μA | 3 | |||
| FB1, FB3 Regulation Voltage | 1.22 | 1.25 | 1.28 | V | 3 | ||
| FB2 Regulation Voltage | -25 | 0 | 25 | mV | 3 | ||
| FB1, FB3 Input Bias Current | -100 | 100 | nA | VFB1 = VFB3 = 1.25V | 3 | ||
| FB2 Input Bias Current | -100 | 100 | nA | VFB2 = 0V | 3 | ||
| REF Regulation Voltage | 1.22 | 1.25 | 1.28 | V | IREF = 50μA | 3 | |
| SW Current Limit | ILIM | 2.8 | 3.6 | A | 3 | ||
| Switching Frequency | fSW | 1 | 1.4 | MHz | 3 | ||
| Maximum Duty Cycle | DM | 85 | 90 | % | 3 | ||
| IN Quiescent Current | 1.3 | 1.6 | mA | VEN > 2V, VFB1 = 1.4V | 3 | ||
| IN Shutdown Current | 0.5 | 1 | μA | VEN ≤ 0.3V | 3 | ||
| REF Load Regulation | 1 | 1.2 | % | 0μA < IREF < 200μA | 3 | ||
| SW Leakage Current | 0.5 | 1 | μA | VSW = 22V | 3 | ||
| IN Undervoltage Lockout Hysteresis | 100 | mV | 3 | ||||
| EN Hysteresis | 100 | mV | 3 | ||||
| EN Input Bias Current | 1 | μA | 3 | ||||
| Soft Start Period | 6 | ms | CCT = 10nF | 3 | |||
| Regulator #2 Turn-On/Turn-Off Delay | 3 | μs | 3 | ||||
| Regulator Turn-On/Turn-Off Delay (label not printed in text) | 6 | ms | CCT = 10nF | 3 | |||
| Error Amplifier Voltage Gain | AvEA | 400 | V/V | 3 | |||
| Error Amplifier Transconductance | GmEA | 1000 | μA/V | 3 | |||
| SW On Resistance | 250 | mΩ | VIN = 5V | 3 | |||
| SW On Resistance | 400 | mΩ | VIN = 3V | 3 | |||
| GL Dropout Voltage | 0.3 | V | VGL = -10V, IGL = -20mA | 3 | |||
| GH Dropout Voltage | 1 | V | VGH = 20V, IGH = 20mA | 3 | |||
| GL Leakage Current | 1 | μA | VIN2 = -15V, VGL = GND | 3 | |||
| GH Leakage Current | 1 | μA | VIN3 = 25V, VGH = GND | 3 | |||
| Thermal Shutdown | 160 | °C | 3 | ||||
| IN Supply Voltage (absolute maximum) | -0.3 | 6 | V | 2 | |||
| SW Voltage (absolute maximum) | -0.3 | 25 | V | 2 | |||
| IN2, GL Voltage (absolute maximum) | -25 | 0.3 | V | 2 | |||
| IN3, GH Voltage (absolute maximum) | -0.3 | 40 | V | 2 | |||
| IN2 to IN3 Voltage (absolute maximum) | -0.3 | 60 | V | 2 | |||
| All Other Pins (absolute maximum) | -0.3 | 6 | V | 2 | |||
| Continuous Power Dissipation (TSSOP16) | PD | 1.4 | W | TA = +25°C | 2 | ||
| Junction Temperature (absolute maximum) | 125 | °C | 2 | ||||
| Lead Temperature (absolute maximum) | 260 | °C | 2 | ||||
| Storage Temperature | -65 | 150 | °C | 2 | |||
| Input Voltage (recommended) | VIN | 2.7 | 5.5 | V | 2 | ||
| Main Output Voltage (recommended) | VMAIN | 22 | V | Minimum is VIN | 2 | ||
| IN2, GL Voltage (recommended) | -20 | 0 | V | 2 | |||
| IN3, GH Voltage (recommended) | 0 | 38 | V | 2 | |||
| Maximum Junction Temperature (recommended) | TJ | 125 | °C | 2 | |||
| Ambient Operating Temperature (free air) | TA | -40 | 85 | °C | Free air temperature, MP1530DM ordering information | 2 | |
| Thermal Resistance Junction-to-Ambient (TSSOP16) | θJA | 90 | °C/W | TSSOP16 | 2 | ||
| Thermal Resistance Junction-to-Case (TSSOP16) | θJC | 30 | °C/W | TSSOP16 | 2 |
CAD (KiCad official)
- Symbol:
MP1530DM-LF-Z - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
mp1530dm-lf-z-etched.step/mp1530dm-lf-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp1530dm-lf-z.step/mp1530dm-lf-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems datasheet (16 pp, sha256
1cf6123489f2f9da, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MP1530DM-LF-Z
**Monolithic Power Systems** · DC-DC Converters · TSSOP-16
MP1530DM-LF-Z from Monolithic Power Systems, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RDY | output | Regulators-not-ready flag that stays high during startup and on a fault, is pulled low once all FB voltages exceed 80% of threshold, and shuts the chip down if a fault persists beyond approximately 6ms (CT = 10nF). |
| 2 | FB1 | input | Step-up converter feedback input, the inverting input of the internal error amplifier, with a regulation voltage of 1.22V to 1.28V. |
| 3 | COMP | output | Step-up converter error-amplifier output, compensated with a series RC network, with a maximum output current of ±100µA. |
| 4 | IN | power_in | Internal power input supplying the device over a 2.7V to 5.5V range, to be bypassed to PGND with a 10µF or greater capacitor. |
| 5 | GND | power_in | Signal ground, which must be connected to PGND as close to the device as possible. |
| 6 | REF | output | 1.25V reference output (1.22V to 1.28V at IREF = 50µA), to be bypassed to GND with a 0.1µF or greater capacitor and used as the top of the negative regulator feedback string. |
| 7 | FB2 | input | Negative linear regulator feedback input with a regulation threshold of GND (±25mV), with the feedback string connected between GL and REF. |
| 8 | FB3 | input | Positive linear regulator feedback input with a 1.25V regulation threshold (1.22V to 1.28V), with the feedback string connected between GH and GND. |
| 9 | EN | input | On/off control input that turns the device on when driven high (VEN HIGH 1.6V minimum) and off when driven low (VEN LOW 0.3V maximum), with EN tied to IN for automatic startup. |
| 10 | GL | power_out | Negative linear regulator output supplying up to 20mA, to be bypassed to GND with a 1µF or greater low-ESR ceramic capacitor. |
| 11 | IN2 | power_in | Negative linear regulator input driven by an inverting charge pump from SW, which can go as low as -20V. |
| 12 | GH | power_out | Positive linear regulator output supplying up to 20mA, to be bypassed to GND with a 1µF or greater low-ESR ceramic capacitor. |
| 13 | IN3 | power_in | Positive linear regulator input driven by a doubling, tripling or quadrupling charge pump from SW, which can go as high as 38V. |
| 14 | PGND | power_in | Power ground and source of the internal 250mΩ N-channel switch, to be connected to GND as close to the device as possible. |
| 15 | SW | output | Step-up converter switch node, the drain of the internal 250mΩ N-channel MOSFET, with an absolute maximum rating of -0.3V to +25V. |
| 16 | CT | passive | Timing capacitor pin connected to GND that sets the soft-start and power-on sequencing delays, with 10nF giving a 6ms soft-start period. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems |
| Package | TSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.7 | | 5.5 | V | | 3 |
| IN Undervoltage Lockout Threshold | VUVLO | 2.25 | | 2.65 | V | IN Rising | 3 |
| EN Input High Voltage | VEN HIGH | 1.6 | | | V | EN Rising | 3 |
| EN Input Low Voltage | | | | 0.3 | V | | 3 |
| COMP Maximum Output Current | | -100 | | 100 | μA | | 3 |
| FB1, FB3 Regulation Voltage | | 1.22 | 1.25 | 1.28 | V | | 3 |
| FB2 Regulation Voltage | | -25 | 0 | 25 | mV | | 3 |
| FB1, FB3 Input Bias Current | | -100 | | 100 | nA | VFB1 = VFB3 = 1.25V | 3 |
| FB2 Input Bias Current | | -100 | | 100 | nA | VFB2 = 0V | 3 |
| REF Regulation Voltage | | 1.22 | 1.25 | 1.28 | V | IREF = 50μA | 3 |
| SW Current Limit | ILIM | 2.8 | | 3.6 | A | | 3 |
| Switching Frequency | fSW | 1 | 1.4 | | MHz | | 3 |
| Maximum Duty Cycle | DM | 85 | 90 | | % | | 3 |
| IN Quiescent Current | | | 1.3 | 1.6 | mA | VEN > 2V, VFB1 = 1.4V | 3 |
| IN Shutdown Current | | | 0.5 | 1 | μA | VEN ≤ 0.3V | 3 |
| REF Load Regulation | | | 1 | 1.2 | % | 0μA < IREF < 200μA | 3 |
| SW Leakage Current | | | 0.5 | 1 | μA | VSW = 22V | 3 |
| IN Undervoltage Lockout Hysteresis | | | 100 | | mV | | 3 |
| EN Hysteresis | | | 100 | | mV | | 3 |
| EN Input Bias Current | | | 1 | | μA | | 3 |
| Soft Start Period | | | 6 | | ms | CCT = 10nF | 3 |
| Regulator #2 Turn-On/Turn-Off Delay | | | 3 | | μs | | 3 |
| Regulator Turn-On/Turn-Off Delay (label not printed in text) | | | 6 | | ms | CCT = 10nF | 3 |
| Error Amplifier Voltage Gain | AvEA | | 400 | | V/V | | 3 |
| Error Amplifier Transconductance | GmEA | | 1000 | | μA/V | | 3 |
| SW On Resistance | | | 250 | | mΩ | VIN = 5V | 3 |
| SW On Resistance | | | 400 | | mΩ | VIN = 3V | 3 |
| GL Dropout Voltage | | | 0.3 | | V | VGL = -10V, IGL = -20mA | 3 |
| GH Dropout Voltage | | | 1 | | V | VGH = 20V, IGH = 20mA | 3 |
| GL Leakage Current | | | 1 | | μA | VIN2 = -15V, VGL = GND | 3 |
| GH Leakage Current | | | 1 | | μA | VIN3 = 25V, VGH = GND | 3 |
| Thermal Shutdown | | | 160 | | °C | | 3 |
| IN Supply Voltage (absolute maximum) | | -0.3 | | 6 | V | | 2 |
| SW Voltage (absolute maximum) | | -0.3 | | 25 | V | | 2 |
| IN2, GL Voltage (absolute maximum) | | -25 | | 0.3 | V | | 2 |
| IN3, GH Voltage (absolute maximum) | | -0.3 | | 40 | V | | 2 |
| IN2 to IN3 Voltage (absolute maximum) | | -0.3 | | 60 | V | | 2 |
| All Other Pins (absolute maximum) | | -0.3 | | 6 | V | | 2 |
| Continuous Power Dissipation (TSSOP16) | PD | | | 1.4 | W | TA = +25°C | 2 |
| Junction Temperature (absolute maximum) | | | | 125 | °C | | 2 |
| Lead Temperature (absolute maximum) | | | | 260 | °C | | 2 |
| Storage Temperature | | -65 | | 150 | °C | | 2 |
| Input Voltage (recommended) | VIN | 2.7 | | 5.5 | V | | 2 |
| Main Output Voltage (recommended) | VMAIN | | | 22 | V | Minimum is VIN | 2 |
| IN2, GL Voltage (recommended) | | -20 | | 0 | V | | 2 |
| IN3, GH Voltage (recommended) | | 0 | | 38 | V | | 2 |
| Maximum Junction Temperature (recommended) | TJ | | | 125 | °C | | 2 |
| Ambient Operating Temperature (free air) | TA | -40 | | 85 | °C | Free air temperature, MP1530DM ordering information | 2 |
| Thermal Resistance Junction-to-Ambient (TSSOP16) | θJA | | 90 | | °C/W | TSSOP16 | 2 |
| Thermal Resistance Junction-to-Case (TSSOP16) | θJC | | 30 | | °C/W | TSSOP16 | 2 |
## CAD (KiCad official)
- Symbol: `MP1530DM-LF-Z`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `mp1530dm-lf-z-etched.step` / `mp1530dm-lf-z-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mp1530dm-lf-z.step` / `mp1530dm-lf-z.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Monolithic Power Systems datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586175417610866688) (16 pp, sha256 `1cf6123489f2f9da`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mp1530dm-lf-z-datasheet.pdf)