# MMBTSA812G

**ST Semtech** · Bipolar (BJT) · SOT-23

MMBTSA812G from ST Semtech, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Base | input | Base terminal of the PNP transistor, with emitter-base voltage rated -VEBO 6 V maximum. |
| 2 | Emitter | passive | Emitter terminal of the PNP transistor, operating within the absolute maximum ratings of -VCEO 50 V and -IC 150 mA. |
| 3 | Collector | passive | Collector terminal of the PNP transistor, rated -VCBO 60 V, -VCEO 50 V and -IC 150 mA with 300 mW total power dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ST Semtech |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Current Gain, Group G | hFE | 200 |  | 400 |  | at -VCE = 6 V, -IC = 1 mA (Group G) | 2 |
| Collector Cutoff Current | -ICBO |  |  | 0.1 | µA | at -VCB = 60 V | 2 |
| Emitter Cutoff Current | -IEBO |  |  | 0.1 | µA | at -VEB = 5 V | 2 |
| Collector Saturation Voltage | -VCE(sat) |  |  | 0.3 | V | at -IC = 100 mA, -IB = 10 mA | 2 |
| Base Emitter Voltage | -VBE | 0.58 |  | 0.68 | V | at -VCE = 6 V, -IC = 1 mA | 2 |
| Collector Base Voltage | -VCBO |  |  | 60 | V |  | 1 |
| Collector Emitter Voltage | -VCEO |  |  | 50 | V |  | 1 |
| Emitter Base Voltage | -VEBO |  |  | 6 | V |  | 1 |
| Collector Current | -IC |  |  | 150 | mA |  | 1 |
| Power Dissipation | Ptot |  |  | 300 | mW |  | 1 |
| Junction Temperature | Tj |  |  | 150 | ℃ |  | 1 |
| Storage Temperature Range | TStg | -55 |  | 150 | ℃ |  | 1 |
| Thermal Resistance from Junction to Ambient | RθJA |  |  | 417 | ℃/W | Device mounted on FR-4 PC board, minimum recommended pad layout | 1 |

## CAD (KiCad official)

- Symbol: `MMBTSA812G`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `mmbtsa812g-etched.step` / `mmbtsa812g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mmbtsa812g.step` / `mmbtsa812g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ST Semtech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603026812486098944) (5 pp, sha256 `9ad4479bdcedce91`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mmbtsa812g-datasheet.pdf)