MMBTRA102SS

ST Semtech · Digital Transistors · SOT-23

MMBTRA102SS from ST Semtech, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Base (Input)	input	Base (input) of the PNP digital transistor, connected through built-in R1 = 10 kΩ with R2 = 10 kΩ to emitter; input voltage rating -30 V, -10 V (-VI).
2	Emitter (Common)	passive	Emitter (common) of the PNP digital transistor, shared with the R2 bias resistor return.
3	Collector (Output)	output	Collector (output) of the transistor, rated for -VO of 50 V and -IO of 100 mA maximum.

Key specifications

Parameter	Value
Manufacturer	ST Semtech
Package	SOT-23
Category	Transistors/Thyristors
Pins	3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DC Current Gain	GI	50				at -VO = 5 V, -IO = 10 mA	2
Output Cutoff Current	-IO(OFF)			500	nA	at -VO = 50 V	2
Input Current	-II			0.88	mA	at -VI = 5 V	2
Output Voltage	-VO(ON)			0.3	V	at -IO = 10 mA, -II = 0.5 mA	2
Input Voltage (ON)	-VI(ON)			2.4	V	at -VO = 0.2 V, -IO = 5 mA	2
Input Voltage (OFF)	-VI(OFF)	1			V	at -VO = 5 V, -IO = 0.1 mA	2
Output Voltage (absolute maximum)	-VO			50	V		1
Input Voltage (absolute maximum)	-VI	-10		30	V		1
Output Current	-IO			100	mA		1
Total Power Dissipation	Ptot			200	mW		1
Junction Temperature	Tj			150	°C		1
Storage Temperature Range	Tstg	-55		150	°C		1
Thermal Resistance, Junction to Ambient	RθJA		625		°C/W	Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout	1
Built-in Bias Resistor R1	R1		10		KΩ		1
Built-in Bias Resistor R2	R2		10		KΩ		1

CAD (KiCad official)

Symbol: MMBTRA102SS
Footprint: Package_TO_SOT_SMD:SOT-23
3D model: SOT-23 (KiCad packages3D, STEP)
3D model files: mmbtra102ss-etched.step / mmbtra102ss-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mmbtra102ss.step / mmbtra102ss.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ST Semtech datasheet (9 pp, sha256 400c353c397e8a23, retrieved 2026-10-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# MMBTRA102SS

**ST Semtech** · Digital Transistors · SOT-23

MMBTRA102SS from ST Semtech, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Base (Input) | input | Base (input) of the PNP digital transistor, connected through built-in R1 = 10 kΩ with R2 = 10 kΩ to emitter; input voltage rating -30 V, -10 V (-VI). |
| 2 | Emitter (Common) | passive | Emitter (common) of the PNP digital transistor, shared with the R2 bias resistor return. |
| 3 | Collector (Output) | output | Collector (output) of the transistor, rated for -VO of 50 V and -IO of 100 mA maximum. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ST Semtech |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Current Gain | GI | 50 |  |  |  | at -VO = 5 V, -IO = 10 mA | 2 |
| Output Cutoff Current | -IO(OFF) |  |  | 500 | nA | at -VO = 50 V | 2 |
| Input Current | -II |  |  | 0.88 | mA | at -VI = 5 V | 2 |
| Output Voltage | -VO(ON) |  |  | 0.3 | V | at -IO = 10 mA, -II = 0.5 mA | 2 |
| Input Voltage (ON) | -VI(ON) |  |  | 2.4 | V | at -VO = 0.2 V, -IO = 5 mA | 2 |
| Input Voltage (OFF) | -VI(OFF) | 1 |  |  | V | at -VO = 5 V, -IO = 0.1 mA | 2 |
| Output Voltage (absolute maximum) | -VO |  |  | 50 | V |  | 1 |
| Input Voltage (absolute maximum) | -VI | -10 |  | 30 | V |  | 1 |
| Output Current | -IO |  |  | 100 | mA |  | 1 |
| Total Power Dissipation | Ptot |  |  | 200 | mW |  | 1 |
| Junction Temperature | Tj |  |  | 150 | °C |  | 1 |
| Storage Temperature Range | Tstg | -55 |  | 150 | °C |  | 1 |
| Thermal Resistance, Junction to Ambient | RθJA |  | 625 |  | °C/W | Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout | 1 |
| Built-in Bias Resistor R1 | R1 |  | 10 |  | KΩ |  | 1 |
| Built-in Bias Resistor R2 | R2 |  | 10 |  | KΩ |  | 1 |

## CAD (KiCad official)

- Symbol: `MMBTRA102SS`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `mmbtra102ss-etched.step` / `mmbtra102ss-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mmbtra102ss.step` / `mmbtra102ss.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ST Semtech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603065789352464384) (9 pp, sha256 `400c353c397e8a23`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mmbtra102ss-datasheet.pdf)