# MM74HCT273WM

**onsemi** · Flip Flops · SOIC-20-300mil

MM74HCT273WM from onsemi, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLEAR | input | Common asynchronous clear input that forces all Q outputs LOW when it is LOW. |
| 2 | Q1 | output | Flip-flop 1 output, takes the level of D1 on the positive-going clock transition; drives 4.0 mA at VCC 4.5V. |
| 3 | D1 | input | Flip-flop 1 data input, transferred to Q1 on the rising clock edge given the specified set-up and hold time. |
| 4 | D2 | input | Flip-flop 2 data input, transferred to Q2 on the rising clock edge given the specified set-up and hold time. |
| 5 | Q2 | output | Flip-flop 2 output, takes the level of D2 on the positive-going clock transition; drives 4.0 mA at VCC 4.5V. |
| 6 | Q3 | output | Flip-flop 3 output, takes the level of D3 on the positive-going clock transition; drives 4.0 mA at VCC 4.5V. |
| 7 | D3 | input | Flip-flop 3 data input, transferred to Q3 on the rising clock edge given the specified set-up and hold time. |
| 8 | D4 | input | Flip-flop 4 data input, transferred to Q4 on the rising clock edge given the specified set-up and hold time. |
| 9 | Q4 | output | Flip-flop 4 output, takes the level of D4 on the positive-going clock transition; drives 4.0 mA at VCC 4.5V. |
| 10 | GND | power_in | Ground, 0 V reference for all voltages. |
| 11 | CLOCK | input | Common positive-edge clock input for all eight flip-flops; input rise/fall time max 500 ns. |
| 12 | Q5 | output | Flip-flop 5 output, takes the level of D5 on the positive-going clock transition; drives 4.0 mA at VCC 4.5V. |
| 13 | D5 | input | Flip-flop 5 data input, transferred to Q5 on the rising clock edge given the specified set-up and hold time. |
| 14 | D6 | input | Flip-flop 6 data input, transferred to Q6 on the rising clock edge given the specified set-up and hold time. |
| 15 | Q6 | output | Flip-flop 6 output, takes the level of D6 on the positive-going clock transition; drives 4.0 mA at VCC 4.5V. |
| 16 | Q7 | output | Flip-flop 7 output, takes the level of D7 on the positive-going clock transition; drives 4.0 mA at VCC 4.5V. |
| 17 | D7 | input | Flip-flop 7 data input, transferred to Q7 on the rising clock edge given the specified set-up and hold time. |
| 18 | D8 | input | Flip-flop 8 data input, transferred to Q8 on the rising clock edge given the specified set-up and hold time. |
| 19 | Q8 | output | Flip-flop 8 output, takes the level of D8 on the positive-going clock transition; drives 4.0 mA at VCC 4.5V. |
| 20 | VCC | power_in | Positive supply voltage, 4.5 V to 5.5 V recommended (absolute max 7.0 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-20-300mil |
| Category | Logic ICs |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VCC), recommended | VCC | 4.5 |  | 5.5 | V |  | 4 |
| Operating Temperature Range (TA) | TA | -40 |  | 85 | °C |  | 4 |
| DC Input or Output Voltage (VIN, VOUT) | VIN, VOUT | 0 |  |  | V | max = VCC (symbolic) | 4 |
| Input Rise or Fall Times (tr, tf) | tr, tf |  |  | 500 | ns |  | 4 |
| Supply Voltage (VCC) | VCC | -0.5 |  | 7 | V |  | 4 |
| DC Input Voltage (VIN) | VIN | -1.5 |  |  | V | max = VCC + 1.5 V | 4 |
| DC Output Voltage (VOUT) | VOUT | -0.5 |  |  | V | max = VCC + 0.5 V | 4 |
| Clamp Diode Current | IIK, IOK | -20 |  | 20 | mA |  | 4 |
| DC Output Current, per Pin | IOUT | -25 |  | 25 | mA |  | 4 |
| DC VCC or GND Current, per Pin | ICC | -50 |  | 50 | mA |  | 4 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 4 |
| Power Dissipation | PD |  |  | 500 | mW | S.O. package only | 4 |
| Lead Temperature | TL |  |  | 260 | °C | Soldering, 10 seconds | 4 |
| Minimum HIGH Level Input Voltage | VIH | 2 | 2 |  | V | VCC 5 V ±10%; guaranteed over TA −55 to 125°C | 4 |
| Maximum LOW Level Input Voltage | VIL |  | 0.8 | 0.8 | V | VCC 5 V ±10%; guaranteed over TA −55 to 125°C | 4 |
| Minimum HIGH Level Output Voltage | VOH | 3.98 | 4.2 |  | V | /IOUT/ 4.0 mA, VCC 4.5 V, VIN VIH or VIL, TA 25°C | 4 |
| Minimum HIGH Level Output Voltage | VOH | 3.84 | 4.2 |  | V | /IOUT/ 4.0 mA, VCC 4.5 V, VIN VIH or VIL, TA −40 to 85°C | 4 |
| Minimum HIGH Level Output Voltage | VOH | 3.7 | 4.2 |  | V | /IOUT/ 4.0 mA, VCC 4.5 V, VIN VIH or VIL, TA −55 to 125°C | 4 |
| Minimum HIGH Level Output Voltage | VOH | 4.98 | 5.2 |  | V | /IOUT/ 4.8 mA, VCC 5.5 V, VIN VIH or VIL, TA 25°C | 4 |
| Minimum HIGH Level Output Voltage | VOH | 4.84 | 5.2 |  | V | /IOUT/ 4.8 mA, VCC 5.5 V, VIN VIH or VIL, TA −40 to 85°C | 4 |
| Minimum HIGH Level Output Voltage | VOH | 4.7 | 5.2 |  | V | /IOUT/ 4.8 mA, VCC 5.5 V, VIN VIH or VIL, TA −55 to 125°C | 4 |
| Maximum LOW Level Output Voltage | VOL |  | 0 | 0.1 | V | /IOUT/ 20 µA, VIN VIH or VIL, TA 25°C | 4 |
| Maximum LOW Level Output Voltage | VOL |  | 0.2 | 0.26 | V | /IOUT/ 4.0 mA, VCC 4.5 V, VIN VIH or VIL, TA 25°C | 4 |
| Maximum LOW Level Output Voltage | VOL |  | 0.2 | 0.33 | V | /IOUT/ 4.0 mA, VCC 4.5 V, VIN VIH or VIL, TA −40 to 85°C | 4 |
| Maximum LOW Level Output Voltage | VOL |  | 0.2 | 0.4 | V | /IOUT/ 4.0 mA, VCC 4.5 V, VIN VIH or VIL, TA −55 to 125°C | 4 |
| Maximum Input Current | IIN | -1 | 0.1 | 1 | µA | VIN VCC or GND, VIH or VIL; guaranteed over TA −55 to 125°C | 4 |
| Maximum Quiescent Supply Current | ICC |  | 8 | 80 | µA | VIN VCC or GND, IOUT 0 µA, TA −40 to 85°C | 4 |
| Maximum Quiescent Supply Current | ICC |  |  | 160 | µA | VIN VCC or GND, IOUT 0 µA, TA −55 to 125°C | 4 |
| Maximum Supply Current (inputs at 2.4 V / 0.5 V) | ICC |  | 0.6 | 0.8 | mA | VIN 2.4 V or 0.5 V (Note 4), TA −40 to 85°C | 4 |
| Maximum Supply Current (inputs at 2.4 V / 0.5 V) | ICC |  |  | 0.9 | mA | VIN 2.4 V or 0.5 V (Note 4), TA −55 to 125°C | 4 |
| Maximum Operating Frequency | fMAX | 27 | 68 |  | MHz | CL 50 pF, VCC 5 V ±10%, tr = tf 6 ns, TA 25°C | 5 |
| Maximum Operating Frequency | fMAX | 21 | 68 |  | MHz | CL 50 pF, VCC 5 V ±10%, tr = tf 6 ns, TA −40 to 85°C | 5 |
| Maximum Operating Frequency | fMAX | 18 | 68 |  | MHz | CL 50 pF, VCC 5 V ±10%, tr = tf 6 ns, TA −55 to 125°C | 5 |
| Maximum Propagation Delay from Clock to Q | tPHL, tPLH |  | 22 | 37 | ns | CL 50 pF, VCC 5 V ±10%, TA 25°C | 5 |
| Maximum Propagation Delay from Clock to Q | tPHL, tPLH |  | 22 | 46 | ns | CL 50 pF, VCC 5 V ±10%, TA −40 to 85°C | 5 |
| Maximum Propagation Delay from Clock to Q | tPHL, tPLH |  | 22 | 56 | ns | CL 50 pF, VCC 5 V ±10%, TA −55 to 125°C | 5 |
| Maximum Propagation Delay from Clear to Q | tPHL, tPLH |  | 25 | 35 | ns | CL 50 pF, VCC 5 V ±10%, TA 25°C | 5 |
| Maximum Propagation Delay from Clear to Q | tPHL, tPLH |  | 25 | 44 | ns | CL 50 pF, VCC 5 V ±10%, TA −40 to 85°C | 5 |
| Maximum Propagation Delay from Clear to Q | tPHL, tPLH |  | 25 | 52 | ns | CL 50 pF, VCC 5 V ±10%, TA −55 to 125°C | 5 |
| Minimum Removal Time, Clear to Clock | tREM | 5 | 1 |  | ns | CL 50 pF, VCC 5 V ±10%, TA 25°C | 5 |
| Minimum Removal Time, Clear to Clock | tREM | 6 | 1 |  | ns | CL 50 pF, VCC 5 V ±10%, TA −40 to 85°C | 5 |
| Minimum Removal Time, Clear to Clock | tREM | 7 | 1 |  | ns | CL 50 pF, VCC 5 V ±10%, TA −55 to 125°C | 5 |
| Minimum Set-Up Time D to Clock | tS | 20 | 6 |  | ns | CL 50 pF, VCC 5 V ±10%, TA 25°C | 5 |
| Minimum Set-Up Time D to Clock | tS | 25 | 6 |  | ns | CL 50 pF, VCC 5 V ±10%, TA −40 to 85°C | 5 |
| Minimum Set-Up Time D to Clock | tS | 30 | 6 |  | ns | CL 50 pF, VCC 5 V ±10%, TA −55 to 125°C | 5 |
| Minimum Hold Time Clock to D | tH | 5 | 3 |  | ns | CL 50 pF, VCC 5 V ±10%, TA 25°C | 5 |
| Minimum Pulse Width Clock or Clear | tW | 16 | 10 |  | ns | CL 50 pF, VCC 5 V ±10%, TA 25°C | 5 |
| Minimum Pulse Width Clock or Clear | tW | 25 | 10 |  | ns | CL 50 pF, VCC 5 V ±10%, TA −40 to 85°C | 5 |
| Minimum Pulse Width Clock or Clear | tW | 30 | 10 |  | ns | CL 50 pF, VCC 5 V ±10%, TA −55 to 125°C | 5 |
| Maximum Output Rise and Fall Time | tTHL, tTLH |  | 11 | 15 | ns | CL 50 pF, VCC 5 V ±10%, TA 25°C | 5 |
| Maximum Output Rise and Fall Time | tTHL, tTLH |  | 11 | 19 | ns | CL 50 pF, VCC 5 V ±10%, TA −40 to 85°C | 5 |
| Maximum Output Rise and Fall Time | tTHL, tTLH |  | 11 | 22 | ns | CL 50 pF, VCC 5 V ±10%, TA −55 to 125°C | 5 |
| Maximum Input Capacitance | CIN |  | 6 | 10 | pF | guaranteed over TA −55 to 125°C | 5 |

## CAD (KiCad official)

- Symbol: `MM74HCT273WM`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `mm74hct273wm-etched.step` / `mm74hct273wm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mm74hct273wm.step` / `mm74hct273wm.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mm74hct273wm-d.pdf) (10 pp, sha256 `e3d30a4b914e9c01`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mm74hct273wm-datasheet.pdf)