MM74HC595MX

{
  "slug": "mm74hc595mx",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "mm74hc595mx",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
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    "README.md",
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    "mm74hc595mx.step",
    "mm74hc595mx.lbr",
    "docs/hero.png",
    "docs/mm74hc595mx-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "mm74hc595mx-hero.glb",
    "mm74hc595mx-hero.overlay.json"
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  "component": {
    "mpn": "MM74HC595MX",
    "manufacturer": "onsemi",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8757029818728886272",
    "parts": {
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      "footprint": "mm74hc595mx.kicad_mod",
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      "model_3d_plain": "mm74hc595mx.glb",
      "model_3d_step": "mm74hc595mx-etched.step",
      "model_3d_step_plain": "mm74hc595mx.step",
      "lbr": "mm74hc595mx.lbr"
    },
    "distributor_links": {
      "lcsc": "C128369",
      "digikey": "MM74HC595MXTR-ND",
      "mouser": "512-MM74HC595MX"
    },
    "distributor_check": {
      "checked_at": "2026-10-09T18:34:07Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "MM74HC595MXTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "512-MM74HC595MX",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "QB",
        "type": "tri_state",
        "description": "Output bit B of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW."
      },
      {
        "number": "2",
        "name": "QC",
        "type": "tri_state",
        "description": "Output bit C of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW."
      },
      {
        "number": "3",
        "name": "QD",
        "type": "tri_state",
        "description": "Output bit D of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW."
      },
      {
        "number": "4",
        "name": "QE",
        "type": "tri_state",
        "description": "Output bit E of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW."
      },
      {
        "number": "5",
        "name": "QF",
        "type": "tri_state",
        "description": "Output bit F of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW."
      },
      {
        "number": "6",
        "name": "QG",
        "type": "tri_state",
        "description": "Output bit G of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW."
      },
      {
        "number": "7",
        "name": "QH",
        "type": "tri_state",
        "description": "Output bit H of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference; all voltages are referenced to ground."
      },
      {
        "number": "9",
        "name": "Q'H",
        "type": "output",
        "description": "Serial data output from the last shift-register stage, used for cascading; it is driven to 0 when SCLR is LOW."
      },
      {
        "number": "10",
        "name": "SCLR",
        "type": "input",
        "description": "Active-LOW shift register clear that resets the shift register and forces Q'H to 0 when asserted LOW."
      },
      {
        "number": "11",
        "name": "SCK",
        "type": "input",
        "description": "Shift register clock; data on SER is shifted in on the positive (LOW-to-HIGH) edge, with a guaranteed shift frequency of DC to 30 MHz."
      },
      {
        "number": "12",
        "name": "RCK",
        "type": "input",
        "description": "Storage register clock; the positive (LOW-to-HIGH) edge transfers the shift register contents to the output latches."
      },
      {
        "number": "13",
        "name": "G",
        "type": "input",
        "description": "Output enable; a HIGH level forces QA through QH into 3-state, and a LOW level enables them."
      },
      {
        "number": "14",
        "name": "SER",
        "type": "input",
        "description": "Serial data input shifted into the first shift-register stage on the SCK rising edge, with 20 ns typical setup and 5 ns hold at VCC = 5 V."
      },
      {
        "number": "15",
        "name": "QA",
        "type": "tri_state",
        "description": "Output bit A of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage, recommended operating range 2 V to 6 V (absolute maximum 6.5 V)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin 9 Q'H is described only as 'Serial Data Output' in the pin definitions, with no 3-state statemen; The VCC pin description gives the recommended range 2 V to 6 V (page 4) and the 6.5 V absolute maxim",
          "1/16 pin names appear NOWHERE in the datasheet text: [\"9:Q'H@p3\"]"
        ],
        "pages_sent": 13,
        "cost_usd": 0.0823,
        "at": "2026-10-09T18:32:00"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8757029818728886272",
        "pages": 13,
        "sha256": "1ee67425ed4574b7",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "zmin_mm": -0.0,
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        "checked": "2026-10-09",
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}