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MM74HC595MX

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onsemi Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MM74HC595MX

onsemi · Shift Registers · SOIC-16

MM74HC595MX from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 QB tri_state Output bit B of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW.
2 QC tri_state Output bit C of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW.
3 QD tri_state Output bit D of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW.
4 QE tri_state Output bit E of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW.
5 QF tri_state Output bit F of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW.
6 QG tri_state Output bit G of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW.
7 QH tri_state Output bit H of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW.
8 GND power_in Ground reference; all voltages are referenced to ground.
9 Q'H output Serial data output from the last shift-register stage, used for cascading; it is driven to 0 when SCLR is LOW.
10 SCLR input Active-LOW shift register clear that resets the shift register and forces Q'H to 0 when asserted LOW.
11 SCK input Shift register clock; data on SER is shifted in on the positive (LOW-to-HIGH) edge, with a guaranteed shift frequency of DC to 30 MHz.
12 RCK input Storage register clock; the positive (LOW-to-HIGH) edge transfers the shift register contents to the output latches.
13 G input Output enable; a HIGH level forces QA through QH into 3-state, and a LOW level enables them.
14 SER input Serial data input shifted into the first shift-register stage on the SCK rising edge, with 20 ns typical setup and 5 ns hold at VCC = 5 V.
15 QA tri_state Output bit A of the 8-bit storage register, which goes to 3-state when G is HIGH and is enabled when G is LOW.
16 VCC power_in Supply voltage, recommended operating range 2 V to 6 V (absolute maximum 6.5 V).

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: MM74HC595MX
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: mm74hc595mx-etched.step / mm74hc595mx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mm74hc595mx.step / mm74hc595mx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (13 pp, sha256 1ee67425ed4574b7, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF