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MIC5014YM-TR
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Microchip Tech Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MIC5014YM-TR
Microchip Tech · Gate Drive ICs · SOIC-8
MIC5014YM-TR from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | V+ | power_in | Supply input (2.75V to 30V operating) that must be decoupled to isolate it from large transients caused by the power MOSFET drain, with 10µF recommended close to pins 1 and 4. |
| 2 | Input | input | TTL-compatible control input that turns on the power MOSFET when taken above (MIC5014) or below (MIC5015) the threshold of 1.0V typical, requiring ~1µA to switch. |
| 3 | Source | passive | Connects to the source lead of the power MOSFET and is the return for the gate clamp zener, and can safely swing to -20V when turning off inductive loads. |
| 4 | Ground | power_in | Ground connection, with the 10µF supply decoupling capacitor recommended close to pins 1 and 4. |
| 5 | Gate | output | Drives and clamps the gate of the power MOSFET, with gate-to-source voltage internally limited to approximately 15V. |
| 6 | NC | unconnected | Not internally connected. |
| 7 | NC | unconnected | Not internally connected. |
| 8 | NC | unconnected | Not internally connected. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (absolute max) | V+ | -20 | 60 | V | 3 | ||
| Input Voltage | -20 | V | -20V to V+ | 3 | |||
| Source Voltage | -20 | V | -20V to V+ | 3 | |||
| Source Current | 50 | mA | 3 | ||||
| Gate Voltage | -20 | 50 | V | 3 | |||
| Junction Temperature | 150 | °C | 3 | ||||
| Storage Temperature | -65 | 150 | °C | 3 | |||
| Lead Temperature | 260 | °C | max soldering time: 10 seconds | 3 | |||
| Thermal Resistance Junction-Ambient (SOIC) | θJA | 170 | °C/W | SOIC | 3 | ||
| Supply Voltage | V+ | 2.75 | 30 | V | 3 | ||
| Ambient Temperature | TA | -40 | 85 | °C | 3 | ||
| Supply Current, VIN De-Asserted | 10 | 25 | µA | V+ = 30V, VIN De-Asserted | 3 | ||
| Supply Current, VIN Asserted | 5 | 10 | mA | V+ = 30V, VIN Asserted | 3 | ||
| Supply Current, VIN Asserted | 60 | 100 | µA | V+ = 5V, VIN Asserted | 3 | ||
| Supply Current, VIN Asserted | 25 | 35 | µA | V+ = 3V, VIN Asserted | 3 | ||
| Logic Input Voltage Threshold, Digital Low Level | VIN | 0.8 | V | 3.0V ≤ V+ ≤ 30V, TA = 25°C | 3 | ||
| Logic Input Voltage Threshold, Digital High Level | VIN | 2 | V | 3.0V ≤ V+ ≤ 30V, TA = 25°C | 3 | ||
| Logic Input Current, VIN Low (MIC5014) | -2 | 0 | µA | 3.0V ≤ V+ ≤ 30V, VIN Low | 3 | ||
| Logic Input Current, VIN High (MIC5014) | 1 | 2 | µA | 3.0V ≤ V+ ≤ 30V, VIN High | 3 | ||
| Input Capacitance | 5 | pF | 3 | ||||
| Gate Enhancement VGATE, VSUPPLY | 4 | 17 | V | 3.0V ≤ V+ ≤ 30V, VIN Asserted | 3 | ||
| Zener Clamp VGATE, VSOURCE | 13 | 15 | 17 | V | 8.0V ≤ V+ ≤ 30V, VIN Asserted | 3 | |
| Gate Turn-on Time | tON | 2.5 | 8 | ms | V+ = 4.5V, CL = 1000pF, time for VGATE to reach V+ + 4V | 3 | |
| Gate Turn-on Time | tON | 90 | 140 | µs | V+ = 12V, CL = 1000pF, time for VGATE to reach V+ + 4V | 3 | |
| Gate Turn-off Time | tOFF | 6 | 30 | µs | V+ = 4.5V, CL = 1000pF, time for VGATE to reach 1V | 3 | |
| Overvoltage Shutdown Threshold | 35 | 37 | 41 | V | 3 |
CAD (KiCad official)
- Symbol:
MIC5014YM-TR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mic5014ym-tr-etched.step/mic5014ym-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mic5014ym-tr.step/mic5014ym-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (12 pp, sha256
4aec02d17a5f2b26, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MIC5014YM-TR
**Microchip Tech** · Gate Drive ICs · SOIC-8
MIC5014YM-TR from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | V+ | power_in | Supply input (2.75V to 30V operating) that must be decoupled to isolate it from large transients caused by the power MOSFET drain, with 10µF recommended close to pins 1 and 4. |
| 2 | Input | input | TTL-compatible control input that turns on the power MOSFET when taken above (MIC5014) or below (MIC5015) the threshold of 1.0V typical, requiring ~1µA to switch. |
| 3 | Source | passive | Connects to the source lead of the power MOSFET and is the return for the gate clamp zener, and can safely swing to -20V when turning off inductive loads. |
| 4 | Ground | power_in | Ground connection, with the 10µF supply decoupling capacitor recommended close to pins 1 and 4. |
| 5 | Gate | output | Drives and clamps the gate of the power MOSFET, with gate-to-source voltage internally limited to approximately 15V. |
| 6 | NC | unconnected | Not internally connected. |
| 7 | NC | unconnected | Not internally connected. |
| 8 | NC | unconnected | Not internally connected. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (absolute max) | V+ | -20 | | 60 | V | | 3 |
| Input Voltage | | -20 | | | V | -20V to V+ | 3 |
| Source Voltage | | -20 | | | V | -20V to V+ | 3 |
| Source Current | | | | 50 | mA | | 3 |
| Gate Voltage | | -20 | | 50 | V | | 3 |
| Junction Temperature | | | | 150 | °C | | 3 |
| Storage Temperature | | -65 | | 150 | °C | | 3 |
| Lead Temperature | | | | 260 | °C | max soldering time: 10 seconds | 3 |
| Thermal Resistance Junction-Ambient (SOIC) | θJA | | 170 | | °C/W | SOIC | 3 |
| Supply Voltage | V+ | 2.75 | | 30 | V | | 3 |
| Ambient Temperature | TA | -40 | | 85 | °C | | 3 |
| Supply Current, VIN De-Asserted | | | 10 | 25 | µA | V+ = 30V, VIN De-Asserted | 3 |
| Supply Current, VIN Asserted | | | 5 | 10 | mA | V+ = 30V, VIN Asserted | 3 |
| Supply Current, VIN Asserted | | | 60 | 100 | µA | V+ = 5V, VIN Asserted | 3 |
| Supply Current, VIN Asserted | | | 25 | 35 | µA | V+ = 3V, VIN Asserted | 3 |
| Logic Input Voltage Threshold, Digital Low Level | VIN | | | 0.8 | V | 3.0V ≤ V+ ≤ 30V, TA = 25°C | 3 |
| Logic Input Voltage Threshold, Digital High Level | VIN | 2 | | | V | 3.0V ≤ V+ ≤ 30V, TA = 25°C | 3 |
| Logic Input Current, VIN Low (MIC5014) | | -2 | | 0 | µA | 3.0V ≤ V+ ≤ 30V, VIN Low | 3 |
| Logic Input Current, VIN High (MIC5014) | | | 1 | 2 | µA | 3.0V ≤ V+ ≤ 30V, VIN High | 3 |
| Input Capacitance | | | 5 | | pF | | 3 |
| Gate Enhancement VGATE, VSUPPLY | | | 4 | 17 | V | 3.0V ≤ V+ ≤ 30V, VIN Asserted | 3 |
| Zener Clamp VGATE, VSOURCE | | 13 | 15 | 17 | V | 8.0V ≤ V+ ≤ 30V, VIN Asserted | 3 |
| Gate Turn-on Time | tON | | 2.5 | 8 | ms | V+ = 4.5V, CL = 1000pF, time for VGATE to reach V+ + 4V | 3 |
| Gate Turn-on Time | tON | | 90 | 140 | µs | V+ = 12V, CL = 1000pF, time for VGATE to reach V+ + 4V | 3 |
| Gate Turn-off Time | tOFF | | 6 | 30 | µs | V+ = 4.5V, CL = 1000pF, time for VGATE to reach 1V | 3 |
| Overvoltage Shutdown Threshold | | 35 | 37 | 41 | V | | 3 |
## CAD (KiCad official)
- Symbol: `MIC5014YM-TR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `mic5014ym-tr-etched.step` / `mic5014ym-tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mic5014ym-tr.step` / `mic5014ym-tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mic5014ym-tr-datasheet.pdf) (12 pp, sha256 `4aec02d17a5f2b26`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mic5014ym-tr-datasheet.pdf)