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MIC4129YME
Public Made by Adomby adom
Microchip Tech Gate Drive ICs, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MIC4129YME
Microchip Tech · Gate Drive ICs · SOIC-8-EP
MIC4129YME from Microchip Tech, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VS | power_in | Supply input (4.5V to 20V operating); duplicate pins 1 and 8 must be externally connected together. |
| 2 | IN | input | Control input accepting logic levels from 2.4V to VS and tolerating swings down to 5V below ground; the MIC4129 output is inverted relative to it. |
| 3 | NC | unconnected | Not connected. |
| 4 | GND | power_in | Ground; duplicate pins 4 and 5 must be externally connected together. |
| 5 | GND | power_in | Ground; duplicate pins 4 and 5 must be externally connected together. |
| 6 | OUT | output | Driver output capable of 6A peak; duplicate pins 6 and 7 must be externally connected together. |
| 7 | OUT | output | Driver output capable of 6A peak; duplicate pins 6 and 7 must be externally connected together. |
| 8 | VS | power_in | Supply input (4.5V to 20V operating); duplicate pins 1 and 8 must be externally connected together. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8-EP |
| Category | Power Management ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic 1 Input Voltage | VIH | 2.4 | 1.9 | V | 3 | ||
| Logic 0 Input Voltage | VIL | 1.5 | 0.8 | V | 3 | ||
| Input Voltage Range | VIN | -5 | V | Max is VS + 0.3 V | 3 | ||
| Input Current | IIN | -10 | 10 | µA | 0 V ≤ VIN ≤ VS | 3 | |
| Low Output Voltage | VOL | 0.025 | V | See Figure 1 | 3 | ||
| Output Resistance, Output Low | RO | 1.4 | 5 | Ω | IOUT = 10 mA, VS = 20 V | 3 | |
| Output Resistance, Output High | RO | 1.5 | 5 | Ω | IOUT = 10 mA, VS = 20 V | 3 | |
| Peak Output Current | IPK | 6 | A | VS = 20 V (See Figure 6) | 3 | ||
| Latch-Up Protection Withstand Reverse Current | IR | 200 | mA | 3 | |||
| Rise Time | tR | 12 | 30 | ns | Test Figure 1, CL = 2200 pF | 3 | |
| Fall Time | tF | 13 | 30 | ns | Test Figure 1, CL = 2200 pF | 3 | |
| Delay Time | tD1 | 45 | 75 | ns | Test Figure 1 | 3 | |
| Delay Time | tD2 | 50 | 75 | ns | Test Figure 1 | 3 | |
| Power Supply Current | IS | 0.45 | 3 | mA | VIN = 3 V | 3 | |
| Power Supply Current | IS | 60 | 400 | µA | VIN = 0 V | 3 | |
| Operating Input Voltage | VS | 4.5 | 20 | V | 3 | ||
| Input Voltage | VIN | -5 | 0.3 | V | VS + 0.3V to GND, 5V | 3 | |
| Input Current | IIN | 50 | mA | VIN > VS | 3 | ||
| Storage Temperature | -65 | 150 | °C | 3 | |||
| Lead Temperature | 300 | °C | 10 sec. | 3 | |||
| Supply Voltage | VS | 4.5 | 20 | V | 3 | ||
| Junction Temperature | TJ | -40 | 125 | °C | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | 4. Devices are ESD sensitive. Handling precautions recommended. Human body model: 1.5kΩ in series with 100pF. Absolute Maximum Ratings (Notes 1, 2 and 3) | 3 |
CAD (KiCad official)
- Symbol:
MIC4129YME - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
mic4129yme-etched.step/mic4129yme-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mic4129yme.step/mic4129yme.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (10 pp, sha256
4737fdd15b3d6c4b, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MIC4129YME
**Microchip Tech** · Gate Drive ICs · SOIC-8-EP
MIC4129YME from Microchip Tech, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VS | power_in | Supply input (4.5V to 20V operating); duplicate pins 1 and 8 must be externally connected together. |
| 2 | IN | input | Control input accepting logic levels from 2.4V to VS and tolerating swings down to 5V below ground; the MIC4129 output is inverted relative to it. |
| 3 | NC | unconnected | Not connected. |
| 4 | GND | power_in | Ground; duplicate pins 4 and 5 must be externally connected together. |
| 5 | GND | power_in | Ground; duplicate pins 4 and 5 must be externally connected together. |
| 6 | OUT | output | Driver output capable of 6A peak; duplicate pins 6 and 7 must be externally connected together. |
| 7 | OUT | output | Driver output capable of 6A peak; duplicate pins 6 and 7 must be externally connected together. |
| 8 | VS | power_in | Supply input (4.5V to 20V operating); duplicate pins 1 and 8 must be externally connected together. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8-EP |
| Category | Power Management ICs |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic 1 Input Voltage | VIH | 2.4 | 1.9 | | V | | 3 |
| Logic 0 Input Voltage | VIL | | 1.5 | 0.8 | V | | 3 |
| Input Voltage Range | VIN | -5 | | | V | Max is VS + 0.3 V | 3 |
| Input Current | IIN | -10 | | 10 | µA | 0 V ≤ VIN ≤ VS | 3 |
| Low Output Voltage | VOL | | | 0.025 | V | See Figure 1 | 3 |
| Output Resistance, Output Low | RO | | 1.4 | 5 | Ω | IOUT = 10 mA, VS = 20 V | 3 |
| Output Resistance, Output High | RO | | 1.5 | 5 | Ω | IOUT = 10 mA, VS = 20 V | 3 |
| Peak Output Current | IPK | | 6 | | A | VS = 20 V (See Figure 6) | 3 |
| Latch-Up Protection Withstand Reverse Current | IR | | 200 | | mA | | 3 |
| Rise Time | tR | | 12 | 30 | ns | Test Figure 1, CL = 2200 pF | 3 |
| Fall Time | tF | | 13 | 30 | ns | Test Figure 1, CL = 2200 pF | 3 |
| Delay Time | tD1 | | 45 | 75 | ns | Test Figure 1 | 3 |
| Delay Time | tD2 | | 50 | 75 | ns | Test Figure 1 | 3 |
| Power Supply Current | IS | | 0.45 | 3 | mA | VIN = 3 V | 3 |
| Power Supply Current | IS | | 60 | 400 | µA | VIN = 0 V | 3 |
| Operating Input Voltage | VS | 4.5 | | 20 | V | | 3 |
| Input Voltage | VIN | -5 | | 0.3 | V | VS + 0.3V to GND, 5V | 3 |
| Input Current | IIN | | | 50 | mA | VIN > VS | 3 |
| Storage Temperature | | -65 | | 150 | °C | | 3 |
| Lead Temperature | | | | 300 | °C | 10 sec. | 3 |
| Supply Voltage | VS | 4.5 | | 20 | V | | 3 |
| Junction Temperature | TJ | -40 | | 125 | °C | | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | | 4. Devices are ESD sensitive. Handling precautions recommended. Human body model: 1.5kΩ in series with 100pF. Absolute Maximum Ratings (Notes 1, 2 and 3) | 3 |
## CAD (KiCad official)
- Symbol: `MIC4129YME`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `mic4129yme-etched.step` / `mic4129yme-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mic4129yme.step` / `mic4129yme.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mic4129yme-datasheet.pdf) (10 pp, sha256 `4737fdd15b3d6c4b`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mic4129yme-datasheet.pdf)