# MIC39101-5.0YM

**Microchip Tech** · Linear Voltage Regulators (LDO) · SO-8

MIC39101-5.0YM from Microchip Tech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | CMOS/TTL-compatible enable input: logic HIGH (2.25V minimum) enables the regulator, logic LOW (0.8V maximum) or open shuts it down, and EN may be tied to VIN with a maximum of +16V. |
| 2 | IN | power_in | Supply input; the operating range is +2.25V to +16V, with an absolute maximum of -20V to +20V. |
| 3 | OUT | power_out | Regulator output; a 10 mA minimum load current is required for proper regulation, and a 10 µF or larger output capacitor with ESR below 2 Ω is recommended for stability. |
| 4 | FLG | output | Open-collector error flag output that goes active LOW when the output drops 5% below its expected value, may sink up to 10 mA, and requires a pull-up resistor to VIN or VOUT; it is inoperative during overtemperature. |
| 5 | GND | power_in | Ground pin, electrically and thermally joined to the die attach paddle; pins 5 through 8 are intended to be soldered to a ground plane to reduce thermal resistance. |
| 6 | GND | power_in | Ground pin, electrically and thermally joined to the die attach paddle; pins 5 through 8 are intended to be soldered to a ground plane to reduce thermal resistance. |
| 7 | GND | power_in | Ground pin, electrically and thermally joined to the die attach paddle; pins 5 through 8 are intended to be soldered to a ground plane to reduce thermal resistance. |
| 8 | GND | power_in | Ground pin, electrically and thermally joined to the die attach paddle; pins 5 through 8 are intended to be soldered to a ground plane to reduce thermal resistance. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SO-8 |
| Category | Power Management ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage accuracy | VOUT | -1 |  | 1 | % | IOUT = 10 mA | 4 |
| Output Voltage accuracy | VOUT | -2 |  | 2 | % | 10 mA ≤ IOUT ≤ 1A, VOUT +1V ≤ VIN ≤ 8V | 4 |
| Line Regulation (25°C column) |  |  |  | 0.06 | % | IOUT = 10 mA, VOUT + 1V ≤ VIN ≤ 16V | 4 |
| Line Regulation (bold, -40°C to +125°C column) |  |  |  | 0.5 | % | IOUT = 10 mA, VOUT + 1V ≤ VIN ≤ 16V | 4 |
| Load Regulation (25°C column) |  |  |  | 0.2 | % | VIN = VOUT + 1V, 10 mA ≤ IOUT ≤ 1A | 4 |
| Load Regulation (bold, -40°C to +125°C column) |  |  |  | 1 | % | VIN = VOUT + 1V, 10 mA ≤ IOUT ≤ 1A | 4 |
| Output Voltage Temperature Coefficient | ∆VOUT/∆T |  | 40 | 100 | ppm/°C | Note 2 | 4 |
| Dropout Voltage | VDO |  | 140 | 200 | mV | IOUT = 100 mA, ∆VOUT = -1% | 4 |
| Dropout Voltage | VDO |  | 250 | 275 | mV | IOUT = 500 mA, ∆VOUT = -1% | 4 |
| Dropout Voltage | VDO |  | 300 | 500 | mV | IOUT = 750 mA, ∆VOUT = -1% | 4 |
| Dropout Voltage (25°C column) | VDO |  | 410 | 550 | mV | IOUT = 1A, ∆VOUT = -1% | 4 |
| Dropout Voltage (guaranteed maximum, bold) | VDO |  |  | 630 | mV | IOUT = 1A, ∆VOUT = -1% | 4 |
| Ground Current | IGND |  | 11 | 20 | mA | IOUT = 1A, VIN = VOUT + 1V | 4 |
| Current Limit | IOUT(LIM) |  | 1.8 | 2.5 | A | VOUT = 0V, VIN = VOUT + 1V | 4 |
| Enable Input Voltage (logic HIGH, On) | VEN | 2.25 |  |  | V | Logic HIGH (On) | 4 |
| Enable Input Voltage (logic LOW, Off) | VEN |  |  | 0.8 | V | Logic LOW (Off) | 4 |
| Enable Input Current | IEN | 1 | 15 | 30 | µA | VEN = 2.25V | 5 |
| Enable Input Current (bold, -40°C to +125°C) | IEN |  |  | 75 | µA | VEN = 2.25V | 5 |
| Enable Input Current (25°C column) | IEN |  |  | 2 | µA | VEN = 0.8V | 5 |
| Enable Input Current (bold, -40°C to +125°C) | IEN |  |  | 4 | µA | VEN = 0.8V | 5 |
| Flag Output Leakage Voltage (25°C column) | IFLG(LEAK) |  | 0.01 | 1 | µA | VOH = 16V | 5 |
| Flag Output Leakage (bold, -40°C to +125°C) | IFLG(LEAK) |  |  | 2 | µA | VOH = 16V | 5 |
| Flag Output Low Voltage (25°C column) | VFLG(DO) |  | 210 | 300 | mV | VIN = 2.250V, IOL = 250 µA, Note 5 | 5 |
| Flag Output Low Voltage (bold, -40°C to +125°C) | VFLG(DO) |  |  | 400 | mV | VIN = 2.250V, IOL = 250 µA, Note 5 | 5 |
| Flag Low Threshold | VFLG | 93 |  |  | % |  | 5 |
| Flag High Threshold | VFLG |  |  | 99.2 | % |  | 5 |
| Junction Operating Temperature Range | TJ | -40 |  | 125 | °C |  | 6 |
| Storage Temperature Range | TS | -65 |  | 150 | °C |  | 6 |
| Lead Temperature |  |  |  | 260 | °C | Soldering, 5s | 6 |
| Supply Voltage (absolute maximum) | VIN | -20 |  | 20 | V |  | 4 |
| Enable Voltage (absolute maximum) | VEN |  |  | 20 | V |  | 4 |
| Supply Voltage (operating range) | VIN | 2.25 |  | 16 | V |  | 4 |
| Enable Voltage (operating range) | VEN |  |  | 16 | V |  | 4 |
| Thermal Resistance, SOIC-8 junction-to-case | JC |  | 20 |  | °C/W |  | 6 |

## CAD (KiCad official)

- Symbol: `MIC39101-5.0YM`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `mic39101-5-0ym-etched.step` / `mic39101-5-0ym-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mic39101-5-0ym.step` / `mic39101-5-0ym.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/mic39101-5-0ym-datasheet.pdf) (24 pp, sha256 `f165c1e273f27a4b`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mic39101-5-0ym-datasheet.pdf)