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MIC39101-3.3YM-TR

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Microchip Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MIC39101-3.3YM-TR

Microchip Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SO-8

MIC39101-3.3YM-TR from Microchip Tech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input CMOS-compatible enable input: logic HIGH enables the regulator, while logic LOW or open puts it in shutdown.
2 IN power_in Supply input, specified for +2.25V to +16V operation with absolute maximum rating of -20V to +20V.
3 OUT power_out Regulated 3.3V output that needs a minimum 10 mA load for proper regulation and an output capacitor of 10 µF or greater with ESR below 2Ω for stability.
4 FLG output Open-collector error flag that goes active LOW when the output drops 5% below its expected value, can sink up to 10 mA, and requires a pull-up resistor to VIN or VOUT.
5 GND power_in Ground pin; pins 5 through 8 are joined to the die attach paddle and should be soldered to a ground plane for thermal performance.
6 GND power_in Ground pin; pins 5 through 8 are joined to the die attach paddle and should be soldered to a ground plane for thermal performance.
7 GND power_in Ground pin; pins 5 through 8 are joined to the die attach paddle and should be soldered to a ground plane for thermal performance.
8 GND power_in Ground pin; pins 5 through 8 are joined to the die attach paddle and should be soldered to a ground plane for thermal performance.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SO-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Voltage accuracy (IOUT = 10 mA) VOUT -1 1 % IOUT = 10 mA 4
Output Voltage accuracy (10 mA to 1 A) VOUT -2 2 % 10 mA ≤ IOUT ≤ 1A, VOUT +1V ≤ VIN ≤ 8V 4
Dropout Voltage VDO 140 200 mV IOUT = 100 mA, ∆VOUT = -1% 4
Dropout Voltage (over temperature) VDO 250 mV IOUT = 100 mA, ∆VOUT = -1% (bold: -40°C ≤ TJ ≤ +125°C) 4
Dropout Voltage VDO 300 500 mV IOUT = 750 mA, ∆VOUT = -1% 4
Dropout Voltage VDO 410 550 mV IOUT = 1A, ∆VOUT = -1% 4
Dropout Voltage (over temperature) VDO 630 mV IOUT = 1A, ∆VOUT = -1% (bold: -40°C ≤ TJ ≤ +125°C) 4
Ground Current IGND 11 20 mA IOUT = 1A, VIN = VOUT + 1V 4
Current Limit IOUT(LIM) 1.8 2.5 A VOUT = 0V, VIN = VOUT + 1V 4
Line Regulation 0.06 % IOUT = 10 mA, VOUT + 1V ≤ VIN ≤ 16V 4
Line Regulation (over temperature) 0.5 % IOUT = 10 mA, VOUT + 1V ≤ VIN ≤ 16V (bold: -40°C ≤ TJ ≤ +125°C) 4
Load Regulation 0.2 % VIN = VOUT + 1V, 10 mA ≤ IOUT ≤ 1A 4
Load Regulation (over temperature) 1 % VIN = VOUT + 1V, 10 mA ≤ IOUT ≤ 1A (bold: -40°C ≤ TJ ≤ +125°C) 4
Output Voltage Temperature Coefficient ∆VOUT/∆T 40 100 ppm/°C Note 2 4
Enable Input Voltage, logic LOW (Off) VEN 0.8 V Logic LOW (Off) 4
Enable Input Voltage, logic HIGH (On) VEN 2.25 V Logic HIGH (On) 4
Enable Input Current IEN 1 15 30 µA VEN = 2.25V 5
Enable Input Current (over temperature) IEN 75 µA VEN = 2.25V (bold: -40°C ≤ TJ ≤ +125°C) 5
Enable Input Current IEN 2 µA VEN = 0.8V 5
Enable Input Current (over temperature) IEN 4 µA VEN = 0.8V (bold: -40°C ≤ TJ ≤ +125°C) 5
Flag Output Leakage Current IFLG(LEAK) 0.01 1 µA VOH = 16V 5
Flag Output Leakage Current (over temperature) IFLG(LEAK) 2 µA VOH = 16V (bold: -40°C ≤ TJ ≤ +125°C) 5
Flag Output Low Voltage VFLG(DO) 210 300 mV VIN = 2.250V, IOL = 250 µA, Note 5 5
Flag Output Low Voltage (over temperature) VFLG(DO) 400 mV VIN = 2.250V, IOL = 250 µA, Note 5 (bold: -40°C ≤ TJ ≤ +125°C) 5
Flag Low Threshold VFLG 93 % of VOUT 5
Flag High Threshold VFLG 99.2 % of VOUT 5
Junction Operating Temperature Range TJ -40 125 °C 6
Storage Temperature Range TS -65 150 °C 6
Lead Temperature 260 °C Soldering, 5s 6
Thermal Resistance, junction-to-case, SOIC-8 θJC 20 °C/W 6
Thermal Resistance, junction-to-ambient, power SO-8 (ideal) θJA 63 °C/W Ideal; varies with copper ground plane 14
Supply Voltage (absolute maximum) VIN -20 20 V 4
Enable Voltage (absolute maximum) VEN 20 V 4
Supply Voltage (operating range) VIN 2.25 16 V 4
Enable Voltage (operating range) VEN 16 V 4
Minimum Load Current IOUT 10 mA Required for proper regulation 13
Output Capacitor ESR ESR 2 Ω COUT ≥ 10 µF 12

CAD (KiCad official)

  • Symbol: MIC39101-3.3YM-TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: mic39101-3-3ym-tr-etched.step / mic39101-3-3ym-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mic39101-3-3ym-tr.step / mic39101-3-3ym-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (24 pp, sha256 f165c1e273f27a4b, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF