component
MIC2133YML-TR
Public Made by Adomby adom
Microchip Tech DC-DC Converters, VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MIC2133YML-TR
Microchip Tech · DC-DC Converters · VQFN-32(5x5)
MIC2133YML-TR from Microchip Tech, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CSN2 | input | Current sense return for Phase 2, connected by Kelvin connection from the low-side FET source to avoid ground drops at high current. |
| 2 | CSP2 | input | Current sense positive for Phase 2, connected by Kelvin connection from the low-side FET drain to avoid ground drops at high current. |
| 3 | CSN1 | input | Current sense return for Phase 1, connected by Kelvin connection from the low-side FET source to avoid ground drops at high current. |
| 4 | CSP1 | input | Current sense positive for Phase 1, connected by Kelvin connection from the low-side FET drain to avoid ground drops at high current. |
| 5 | ILIM | input | Current limit adjust input; a resistor from ILIM to AGND sets the current limit threshold shared by both channels. |
| 6 | CSH | output | Average current sense voltage output used for current sharing, AVP droop and telemetry, with 100 pF connected from CSH to AGND. |
| 7 | EN | input | Active-high enable input with a 1.2V precise threshold, 75V compatible, which disables the buck output when pulled to GND. |
| 8 | VIN | power_in | Input voltage to the controller, connected to VIN through a 1.21 ohm resistor with a 1 µF capacitor to PGND. |
| 9 | VDD | power_out | 5V LDO output that biases the control logic, requiring a minimum 2.2 µF low-ESR ceramic capacitor to AGND. |
| 10 | AGND | power_in | Analog ground and reference node for all control logic, to be connected to PGND at one point. |
| 11 | EXTVDD | power_in | Auxiliary LDO input that bypasses the internal 5V LDO when connected to a supply higher than 4.7V (typ.), or left unconnected or grounded when unused. |
| 12 | PSH | input | Phase shedding threshold programming pin, where a resistor from PSH to AGND sets the threshold through its voltage drop. |
| 13 | TEMP | output | Die junction temperature sense output from an internal diode, requiring a 1 µF capacitor to AGND. |
| 14 | OUTS | input | Output voltage sense pin, connected through a 10 kΩ resistor with a 100 nF decoupling capacitor for VOUT up to 5V, or through a resistive divider for VOUT above 5V. |
| 15 | DR | output | Gate driver output for the output OVP discharge MOSFET, which goes high after an overvoltage event longer than 12 µs and requires EN or VIN cycling to restart. |
| 16 | BST1 | power_in | Phase 1 bootstrap supply input for the high-side driver, connected with a 0.1 µF low-ESR ceramic capacitor to SW1. |
| 17 | DH1 | output | Phase 1 high-side gate driver output, connected to the Phase 1 high-side MOSFET gate. |
| 18 | SW1 | output | Phase 1 switch node output, connected to one terminal of the Phase 1 inductor. |
| 19 | DL1 | output | Phase 1 low-side gate driver output, connected to the Phase 1 low-side MOSFET gate. |
| 20 | PGND | power_in | Power ground and return path for the low-side MOSFET current and driver, to be connected together and to the power ground plane. |
| 21 | PVDD | power_in | Supply pin for the low-side MOSFET driver, connected to VDD through a 2.2 ohm series resistor with a minimum 4.7 µF low-ESR capacitor to PGND. |
| 22 | DL2 | output | Phase 2 low-side gate driver output, connected to the Phase 2 low-side MOSFET gate. |
| 23 | SW2 | output | Phase 2 switch node output, connected to one terminal of the Phase 2 inductor. |
| 24 | DH2 | output | Phase 2 high-side gate driver output, connected to the Phase 2 high-side MOSFET gate. |
| 25 | BST2 | power_in | Phase 2 bootstrap supply input for the high-side driver, connected with a 0.1 µF low-ESR ceramic capacitor to SW2. |
| 26 | PG | output | Open-drain power good output that is pulled to ground below 80% of target and needs a 10 kΩ pull-up to VDD for a high level above 90%. |
| 27 | RIP_INJ | passive | Ripple injection node connected through a series RC network to FBS, with a preposition resistor to AGND to set its steady-state voltage. |
| 28 | FBS | input | Remote feedback input connected to the midpoint of the resistor divider from output voltage to GFB to set the output voltage. |
| 29 | GFB | input | Ground feedback remote sense pin, connected with Kelvin sense directly across the output capacitor ground. |
| 30 | SS | passive | Soft start adjustment pin, where a capacitor from SS to AGND sets the soft start time. |
| 31 | FREQ | input | Frequency programming input, connected to ground through a resistor that sets the same switching frequency for each phase. |
| 32 | DROOP | output | Analog droop output for adaptive voltage positioning, where a resistor from DROOP to the feedback divider sets the droop, and its voltage is proportional to inductor current for loads above 0A. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | VQFN-32(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 8 | 75 | V | 5 | ||
| Quiescent Supply Current | IQ | 5000 | 8000 | µA | VFBS = +1.5V | 5 | |
| Shutdown Current | ISD | 25 | 50 | µA | VEN = 0V | 5 | |
| VDD Voltage Range | VDD | 4.7 | 5.1 | 5.4 | V | VIN = 8V to 75V, IVDD = 20 mA (Note 5) | 5 |
| VDD Undervoltage Lockout Upper Threshold | VDDUV_R | 3.7 | 4.2 | 4.5 | V | VDD rising | 5 |
| VDD Regulation | ΔVDD | 1 | 2.5 | % | VIN = 24V, IVDD from 1 mA to 40 mA (Note 5) | 5 | |
| VDD Regulator Dropout Voltage | VDROP_VDD | 0.8 | 1.05 | V | VIN = 5.5V, IVDD = 25 mA | 5 | |
| EXTVDD Switchover Voltage | VSO_EVDD | 4.5 | 4.7 | 4.9 | V | VIN = 24V, EXTVDD rising, IVDD = 40 mA | 5 |
| Soft Start Source Current | ISS | 0.8 | 1.2 | 1.7 | µA | 5 | |
| Output Voltage Adjustable Range | VOUT | 0.6 | 28 | V | Note 2 | 5 | |
| Feedback Regulation Voltage | VFBS-GFB | 0.593 | 0.6 | 0.606 | V | Measured with EA in servo loop | 5 |
| Enable Upper Threshold Voltage | VEN_TH | 1.05 | 1.2 | 1.36 | V | Enable Rising | 5 |
| Enable Bias Current | IEN | 100 | 200 | nA | VEN = 12V | 5 | |
| Nominal Switching Frequency per Phase | fSWNOM_PH | 400 | 500 | 600 | kHz | VIN = 12V, VOUTS = 5V, RFREQ = 40.2 kΩ | 6 |
| ILIM Source Current | ICL | 8.3 | 9.6 | 10.56 | µA | 6 | |
| Nominal Current Limit Threshold Voltage per Phase | VILIM_TH | 139 | 156 | 174 | mV | RILIM = 60.4 kΩ | 6 |
| Negative Current Limit Threshold Voltage | VILIM_NTH | 60 | 75 | 90 | mV | RILIM = 60.4 kΩ | 6 |
| Zero-Crossing Detection Threshold | VZCD_TH | -10 | -4 | -0.6 | mV | 6 | |
| CSH Operating Point | VCSH_OP | 1.154 | 1.19 | 1.244 | V | VCSN1 = VCSN2 = VCSP1 = VCSP2 = 0V | 6 |
| Current Sense Input Voltage Range | VCS | -120 | 120 | mV | -40ºC ≤ TJ ≤ +125ºC | 6 | |
| Ripple Injection Pulse Width | tPW(RI) | 100 | 120 | ns | 7 | ||
| Ripple Injection Prepositioning Current | IBIAS | 4.8 | 6 | µA | Force VRIPINJ = 0V, VSS = 0V, measure current | 7 | |
| DHx On-Resistance, High State | RON_DHH | 2.5 | 4.5 | Ω | ISOURCE = 0.1A | 7 | |
| DHx On-Resistance, Low State | RON_DHL | 1.6 | 3.2 | Ω | ISINK = 0.1A | 7 | |
| DLx On-Resistance, High State | RON_DLH | 2.5 | 4.5 | Ω | ISOURCE = 0.1A | 7 | |
| DLx On-Resistance, Low State | RON_DLL | 0.8 | 1.5 | Ω | ISINK = 0.1A | 7 | |
| BST Leakage | ILEAK(BST) | 10 | µA | VBST = 75V | 7 | ||
| VIN Leakage | ILEAK(VIN) | 60 | µA | VIN = 70V | 7 | ||
| SW Leakage | ILEAK(SW) | 20 | µA | VSW = 70V | 7 | ||
| PG Threshold from Low to High | VPG_TH | 83 | 88 | 94 | %VOUT | VFBS rising | 7 |
| PG Low State Voltage | VPG_L | 70 | 200 | mV | VFBS < 90% x VNOM, IPG = 1 mA | 7 | |
| PG Leakage Current | ILEAK(PG) | 500 | nA | VPG = 5.5V | 7 | ||
| Phase Shedding Exit Threshold | VPSH_EXIT | 170 | 244 | 300 | mV | VPSH = 0.96V, VDROOP ramp-up (Note 3) | 8 |
| Phase Shedding Entry Threshold | VPSH_ENTRY | 135 | 195 | 240 | mV | VPSH = 0.96V, VDROOP ramp-down (Note 3) | 8 |
| PSH Current | IPSH | 9 | 10 | 11 | µA | 8 | |
| OVP Threshold | VOVP_TH | 0.64 | 0.67 | 0.7 | V | OVP is activated after UVLO goes high and VFBS soft start | 8 |
| Supply Voltage (VIN) operating | VIN | 8 | 75 | V | Operating Ratings | 4 | |
| PVDD, VDD Pin Voltage | VDD | 4.5 | 5.5 | V | Operating Ratings | 4 | |
| OUTS Pin Voltage | OUTS | 0.6 | 5.5 | V | Operating Ratings | 4 | |
| EXTVDD Pin Voltage | EXTVDD | 0 | 13 | V | Operating Ratings | 4 | |
| Enable Input Voltage | VEN | 0 | 75 | V | 0V to VIN | 4 | |
| Junction Temperature (operating) | TJ | -40 | 125 | °C | Operating Ratings | 4 | |
| VIN to AGND | VIN | -0.3 | 76 | V | 4 | ||
| VDD, OUTS to AGND | VDD | -0.3 | 6 | V | 4 | ||
| PVDD to PGND | PVDD | -0.3 | 6 | V | 4 | ||
| BST1 to SW1, BST2 to SW2 | VBST-SW | -0.3 | 6 | V | 4 | ||
| EXTVDD to AGND | EXTVDD | -0.3 | 14 | V | 4 | ||
| CSN1, CSN2, GFB, PGND to AGND | -0.3 | 0.3 | V | 4 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 4 | |||
| Storage Temperature | TS | -65 | 150 | °C | 4 | ||
| Lead Temperature | TLEAD | 300 | °C | Soldering, 10s | 4 | ||
| Thermal Resistance Junction to Case, 5x5 32-Lead VQFN | θJC | 2 | °C/W | Junction to Case | 9 | ||
| Thermal Resistance Junction to Ambient, 5x5 32-Lead VQFN | θJA | 34 | °C/W | Junction to Ambient | 9 |
CAD (KiCad official)
- Symbol:
MIC2133YML-TR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
mic2133yml-tr-etched.step/mic2133yml-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mic2133yml-tr.step/mic2133yml-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (50 pp, sha256
037b44cdcecc8130, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).