component
MIC2128YML-TR
Public Made by Adomby adom
Microchip Tech DC-DC Converters, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MIC2128YML-TR
Microchip Tech · DC-DC Converters · VQFN-16-EP(3x3)
MIC2128YML-TR from Microchip Tech, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PG | output | Open-drain Power Good output; connect to VDD through a pull-up resistor, and it is low when FB is 10% below the 0.6V reference. |
| 2 | ILIM | passive | Current limit setting pin; connect a resistor from ILIM to SW to set the current limit (rated 0V to VIN operating, -0.3V to +76V absolute max). |
| 3 | SW | bidirectional | Switch node connecting the high-side MOSFET source and low-side MOSFET drain, returns the high-side gate driver and senses low-side current for negative current limit. |
| 4 | BST | passive | Bootstrap capacitor pin supplying the high-side N-MOSFET driver; connect a minimum 0.1 µF low ESR ceramic capacitor between BST and SW. |
| 5 | DH | output | High-side N-MOSFET gate driver output; connect to the gate of the external high-side N-MOSFET. |
| 6 | PGND | power_in | Power ground, return for the low-side gate driver and reference for the current limit comparator; connect to the low-side MOSFET source and PVDD bypass capacitor return. |
| 7 | DL | output | Low-side N-MOSFET gate driver output; connect to the gate of the external low-side N-MOSFET. |
| 8 | PVDD | power_out | Internal high voltage LDO output supplying the low-side and floating high-side MOSFET drivers; connect a minimum 4.7 µF low ESR ceramic capacitor to PGND. |
| 9 | EXTVDD | power_in | Supply to the internal low voltage LDO; connect to the buck output if between 4.7V and 14V (operating 0V to 13.2V) and bypass with a minimum 1 µF ceramic capacitor. |
| 10 | EN | input | Enable logic input; logic high enables the converter and logic low disables it (0V to VIN operating). |
| 11 | FREQ | input | Switching frequency programming input; connect to the midpoint of a resistor divider between VIN and AGND, or tie to VIN for 800 kHz. |
| 12 | SS | passive | Soft-start time setting pin; connect a ceramic capacitor from SS to AGND to set the output soft-start time. |
| 13 | FB | input | Feedback input to the transconductance amplifier, regulated to 0.6V; connect to the midpoint of the resistor divider between output and AGND. |
| 14 | AGND | power_in | Analog ground reference for the internal analog control circuits; connect to PGND at one point on the PCB. |
| 15 | VDD | power_in | Supply for the internal analog circuits; connect to PVDD through a low pass filter with a minimum 4.7 µF low ESR ceramic capacitor to AGND. |
| 16 | VIN | power_in | Supply input to the internal high voltage LDO, 4.5V to 75V; bypass to PGND with a minimum 0.1 µF low ESR ceramic capacitor. |
| 17 | EP | passive | Exposed thermal pad; connect to the AGND copper plane to improve thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | VQFN-16-EP(3x3) |
| Category | Power Supply Chip |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VVIN | 4.5 | 5.5 | V | PVDD and VDD shorted to VIN (VPVDD = VVIN = VVDD) | 4 | |
| Input Voltage Range | VVIN | 5.5 | 75 | V | 4 | ||
| Quiescent Supply Current | IQ | 1.4 | 1.8 | mA | VFB = 1.5V, no switching | 4 | |
| Shutdown Supply Current | IVIN(SHDN) | 0.1 | 5 | µA | EN = Low | 4 | |
| Shutdown Supply Current | IVIN(SHDN) | 30 | 60 | µA | EN = Low, VIN = VDD = 5.5V | 4 | |
| PVDD Output Voltage | VPVDD | 4.8 | 5.1 | 5.4 | V | VVIN = 7V to 75V, IPVDD = 10 mA | 4 |
| VDD UVLO Threshold | VVDD_UVLO_Rise | 3.7 | 4.2 | 4.5 | V | VDD rising | 4 |
| EXTVDD Bypass Threshold | VEXTVDD_Rise | 4.4 | 4.6 | 4.85 | V | EXTVDD rising | 4 |
| Feedback Reference Voltage | VREF | 0.597 | 0.6 | 0.603 | V | TJ = 25°C | 4 |
| Feedback Reference Voltage | VREF | 0.594 | 0.6 | 0.606 | V | -40°C ≤ TJ ≤ 125°C | 4 |
| FB Bias Current | IFB | 50 | 500 | nA | VFB = 0.6V | 4 | |
| EN Logic Level High | VEN_H | 1.6 | V | 4 | |||
| EN Logic Level Low | VEN_L | 0.6 | V | 4 | |||
| EN Bias Current | IEN | 6 | 30 | µA | VEN = 12V | 4 | |
| Switching Frequency | fSW | 230 | 270 | 300 | kHz | VFREQ = 33% of VVIN, VVIN = 12V | 4 |
| Switching Frequency | fSW | 800 | kHz | VFREQ = VVIN, VVIN = 12V | 4 | ||
| Minimum OFF Time | tOFF(MIN) | 150 | 230 | 350 | ns | 4 | |
| Current-Limit Comparator Offset | VOFFSET | -15 | 0 | 15 | mV | VFB = 0.59V | 4 |
| ILIM Source Current | ICL | 85 | 100 | 115 | µA | VFB = 0.59V | 5 |
| DH On-Resistance, High State | RDH(PULL-UP) | 2 | 3 | Ω | 5 | ||
| DH On-Resistance, Low State | RDH(PULL_DOWN) | 2 | 4 | Ω | 5 | ||
| DL On-Resistance, High State | RDL(PULL-UP) | 2 | 4 | Ω | 5 | ||
| DL On-Resistance, Low State | RDL(PULL_DOWN) | 0.36 | 0.8 | Ω | 5 | ||
| BST Leakage | ILK(BST) | 30 | µA | 5 | |||
| VIN Leakage | ILK(VIN) | 50 | µA | 5 | |||
| SW Leakage | ILK(SW) | 50 | µA | 5 | |||
| PG Threshold Voltage | VPG_Rise | 85 | 95 | %VOUT | VFB rising | 5 | |
| PG Low Voltage | VOL_PG | 70 | 200 | mV | VFB < 90% × VNOM, IPG = 1 mA | 5 | |
| VIN, FREQ, ILIM, SW to PGND | -0.3 | 76 | V | 3 | |||
| VSW to PGND (Transient < 50 ns) | VSW | -5 | V | Transient < 50 ns | 3 | ||
| VDD, PVDD, FB, PG, SS to AGND | -0.3 | 6 | V | 3 | |||
| EXTVDD to AGND | -0.3 | 16 | V | 3 | |||
| BST to SW | -0.3 | 6 | V | 3 | |||
| BST to AGND | -0.3 | 82 | V | 3 | |||
| EN to AGND | -0.3 | V | max is VIN + 0.3V | 3 | |||
| DH, DL to AGND | -0.3 | V | max is VDD + 0.3V | 3 | |||
| PGND to AGND | -0.3 | 0.3 | V | 3 | |||
| Junction Temperature | TJ | 150 | °C | 3 | |||
| Storage Temperature | TS | -65 | 150 | °C | 3 | ||
| Lead Temperature | TLEAD | 260 | °C | Soldering, 10s | 3 | ||
| ESD Rating | 1000 | V | Human body model, 1.5 kΩ in series with 100 pF | 3 | |||
| Supply Voltage | VIN | 4.5 | 75 | V | 3 | ||
| SW, FREQ, ILIM, EN | 0 | V | max is VIN | 3 | |||
| EXTVDD | 0 | 13.2 | V | 3 | |||
| Operating Junction Temperature | TJ | -40 | 125 | °C | 3 | ||
| Junction to Ambient | θJA | 50.8 | °C/W | 3 mm × 3 mm QFN-16 | 3 | ||
| Junction to Case | θJC | 25.3 | °C/W | 3 mm × 3 mm QFN-16 | 3 |
CAD (KiCad official)
- Symbol:
MIC2128YML-TR - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
mic2128yml-tr-etched.step/mic2128yml-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mic2128yml-tr.step/mic2128yml-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (36 pp, sha256
8d4e2fa21b3a8141, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MIC2128YML-TR
**Microchip Tech** · DC-DC Converters · VQFN-16-EP(3x3)
MIC2128YML-TR from Microchip Tech, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PG | output | Open-drain Power Good output; connect to VDD through a pull-up resistor, and it is low when FB is 10% below the 0.6V reference. |
| 2 | ILIM | passive | Current limit setting pin; connect a resistor from ILIM to SW to set the current limit (rated 0V to VIN operating, -0.3V to +76V absolute max). |
| 3 | SW | bidirectional | Switch node connecting the high-side MOSFET source and low-side MOSFET drain, returns the high-side gate driver and senses low-side current for negative current limit. |
| 4 | BST | passive | Bootstrap capacitor pin supplying the high-side N-MOSFET driver; connect a minimum 0.1 µF low ESR ceramic capacitor between BST and SW. |
| 5 | DH | output | High-side N-MOSFET gate driver output; connect to the gate of the external high-side N-MOSFET. |
| 6 | PGND | power_in | Power ground, return for the low-side gate driver and reference for the current limit comparator; connect to the low-side MOSFET source and PVDD bypass capacitor return. |
| 7 | DL | output | Low-side N-MOSFET gate driver output; connect to the gate of the external low-side N-MOSFET. |
| 8 | PVDD | power_out | Internal high voltage LDO output supplying the low-side and floating high-side MOSFET drivers; connect a minimum 4.7 µF low ESR ceramic capacitor to PGND. |
| 9 | EXTVDD | power_in | Supply to the internal low voltage LDO; connect to the buck output if between 4.7V and 14V (operating 0V to 13.2V) and bypass with a minimum 1 µF ceramic capacitor. |
| 10 | EN | input | Enable logic input; logic high enables the converter and logic low disables it (0V to VIN operating). |
| 11 | FREQ | input | Switching frequency programming input; connect to the midpoint of a resistor divider between VIN and AGND, or tie to VIN for 800 kHz. |
| 12 | SS | passive | Soft-start time setting pin; connect a ceramic capacitor from SS to AGND to set the output soft-start time. |
| 13 | FB | input | Feedback input to the transconductance amplifier, regulated to 0.6V; connect to the midpoint of the resistor divider between output and AGND. |
| 14 | AGND | power_in | Analog ground reference for the internal analog control circuits; connect to PGND at one point on the PCB. |
| 15 | VDD | power_in | Supply for the internal analog circuits; connect to PVDD through a low pass filter with a minimum 4.7 µF low ESR ceramic capacitor to AGND. |
| 16 | VIN | power_in | Supply input to the internal high voltage LDO, 4.5V to 75V; bypass to PGND with a minimum 0.1 µF low ESR ceramic capacitor. |
| 17 | EP | passive | Exposed thermal pad; connect to the AGND copper plane to improve thermal performance. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | VQFN-16-EP(3x3) |
| Category | Power Supply Chip |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VVIN | 4.5 | | 5.5 | V | PVDD and VDD shorted to VIN (VPVDD = VVIN = VVDD) | 4 |
| Input Voltage Range | VVIN | 5.5 | | 75 | V | | 4 |
| Quiescent Supply Current | IQ | | 1.4 | 1.8 | mA | VFB = 1.5V, no switching | 4 |
| Shutdown Supply Current | IVIN(SHDN) | | 0.1 | 5 | µA | EN = Low | 4 |
| Shutdown Supply Current | IVIN(SHDN) | | 30 | 60 | µA | EN = Low, VIN = VDD = 5.5V | 4 |
| PVDD Output Voltage | VPVDD | 4.8 | 5.1 | 5.4 | V | VVIN = 7V to 75V, IPVDD = 10 mA | 4 |
| VDD UVLO Threshold | VVDD_UVLO_Rise | 3.7 | 4.2 | 4.5 | V | VDD rising | 4 |
| EXTVDD Bypass Threshold | VEXTVDD_Rise | 4.4 | 4.6 | 4.85 | V | EXTVDD rising | 4 |
| Feedback Reference Voltage | VREF | 0.597 | 0.6 | 0.603 | V | TJ = 25°C | 4 |
| Feedback Reference Voltage | VREF | 0.594 | 0.6 | 0.606 | V | -40°C ≤ TJ ≤ 125°C | 4 |
| FB Bias Current | IFB | | 50 | 500 | nA | VFB = 0.6V | 4 |
| EN Logic Level High | VEN_H | 1.6 | | | V | | 4 |
| EN Logic Level Low | VEN_L | | | 0.6 | V | | 4 |
| EN Bias Current | IEN | | 6 | 30 | µA | VEN = 12V | 4 |
| Switching Frequency | fSW | 230 | 270 | 300 | kHz | VFREQ = 33% of VVIN, VVIN = 12V | 4 |
| Switching Frequency | fSW | | 800 | | kHz | VFREQ = VVIN, VVIN = 12V | 4 |
| Minimum OFF Time | tOFF(MIN) | 150 | 230 | 350 | ns | | 4 |
| Current-Limit Comparator Offset | VOFFSET | -15 | 0 | 15 | mV | VFB = 0.59V | 4 |
| ILIM Source Current | ICL | 85 | 100 | 115 | µA | VFB = 0.59V | 5 |
| DH On-Resistance, High State | RDH(PULL-UP) | | 2 | 3 | Ω | | 5 |
| DH On-Resistance, Low State | RDH(PULL_DOWN) | | 2 | 4 | Ω | | 5 |
| DL On-Resistance, High State | RDL(PULL-UP) | | 2 | 4 | Ω | | 5 |
| DL On-Resistance, Low State | RDL(PULL_DOWN) | | 0.36 | 0.8 | Ω | | 5 |
| BST Leakage | ILK(BST) | | | 30 | µA | | 5 |
| VIN Leakage | ILK(VIN) | | | 50 | µA | | 5 |
| SW Leakage | ILK(SW) | | | 50 | µA | | 5 |
| PG Threshold Voltage | VPG_Rise | 85 | | 95 | %VOUT | VFB rising | 5 |
| PG Low Voltage | VOL_PG | | 70 | 200 | mV | VFB < 90% × VNOM, IPG = 1 mA | 5 |
| VIN, FREQ, ILIM, SW to PGND | | -0.3 | | 76 | V | | 3 |
| VSW to PGND (Transient < 50 ns) | VSW | -5 | | | V | Transient < 50 ns | 3 |
| VDD, PVDD, FB, PG, SS to AGND | | -0.3 | | 6 | V | | 3 |
| EXTVDD to AGND | | -0.3 | | 16 | V | | 3 |
| BST to SW | | -0.3 | | 6 | V | | 3 |
| BST to AGND | | -0.3 | | 82 | V | | 3 |
| EN to AGND | | -0.3 | | | V | max is VIN + 0.3V | 3 |
| DH, DL to AGND | | -0.3 | | | V | max is VDD + 0.3V | 3 |
| PGND to AGND | | -0.3 | | 0.3 | V | | 3 |
| Junction Temperature | TJ | | | 150 | °C | | 3 |
| Storage Temperature | TS | -65 | | 150 | °C | | 3 |
| Lead Temperature | TLEAD | | | 260 | °C | Soldering, 10s | 3 |
| ESD Rating | | | | 1000 | V | Human body model, 1.5 kΩ in series with 100 pF | 3 |
| Supply Voltage | VIN | 4.5 | | 75 | V | | 3 |
| SW, FREQ, ILIM, EN | | 0 | | | V | max is VIN | 3 |
| EXTVDD | | 0 | | 13.2 | V | | 3 |
| Operating Junction Temperature | TJ | -40 | | 125 | °C | | 3 |
| Junction to Ambient | θJA | | 50.8 | | °C/W | 3 mm × 3 mm QFN-16 | 3 |
| Junction to Case | θJC | | 25.3 | | °C/W | 3 mm × 3 mm QFN-16 | 3 |
## CAD (KiCad official)
- Symbol: `MIC2128YML-TR`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `mic2128yml-tr-etched.step` / `mic2128yml-tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mic2128yml-tr.step` / `mic2128yml-tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mic2128yml-tr-datasheet.pdf) (36 pp, sha256 `8d4e2fa21b3a8141`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mic2128yml-tr-datasheet.pdf)