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MFS5600AMMA0ES

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NXP Semicon Power Management - Specialized, HVQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)mfs5600amma0esfactory-2.0.0extractor-text

Verified MFS5600AMMA0ES

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MFS5600AMMA0ES · HVQFN-32(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 119-page datasheet
  • ✓distributor: lcsc C3189144, digikey 568-MFS5600AMMA0ES-ND, mouser 771-MFS5600AMMA0ES
  • ✓family: HVQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-l7gz2nev/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ mfs5600amma0es.kicad_sym✓ mfs5600amma0es.kicad_mod✓ mfs5600amma0es.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers mfs5600amma0es: viewers · Ray 4d ago
mfs5600amma0es-etched.glb Publish 0.1.0 · Ray 4d ago
mfs5600amma0es-etched.step mfs5600amma0es: factory component page (tier=mfr) · Ray 4d ago
mfs5600amma0es-hero.glb mfs5600amma0es: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
mfs5600amma0es-hero.overlay.json Publish 0.1.0 · Ray 4d ago
mfs5600amma0es.glb Publish 0.1.0 · Ray 4d ago
mfs5600amma0es.kicad_mod Publish 0.1.0 · Ray 4d ago
mfs5600amma0es.kicad_sym Publish 0.1.0 · Ray 4d ago
mfs5600amma0es.lbr Publish 0.1.0 · Ray 4d ago
mfs5600amma0es.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier mfr, 33 pins · Ray 4d ago

MFS5600AMMA0ES

NXP Semicon · Power Management - Specialized · HVQFN-32(5x5)

MFS5600AMMA0ES from NXP Semicon, in a HVQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDIO power_in I2C I/O driver supply, connect to 1.8 V or 3.3 V and bypass with 0.1 µF; abs max -0.3 V to 5.5 V.
2 SCL input I2C clock line, pulled up to VDDIO on the board; abs max -0.3 V to 5.5 V.
3 SDA bidirectional I2C data line, pulled up to VDDIO on the board; abs max -0.3 V to 5.5 V.
4 GPIO1/VDDOTP bidirectional General-purpose input/output pin, used as VDDOTP during development; abs max -0.3 V to 10 V.
5 SW2COMP passive SW2 compensation pin, connect to external compensation network; abs max -0.3 V to 5.5 V.
6 SW2FB input SW2 output voltage feedback, internal or external divider for outputs ≤ 5.5 V and external divider for outputs > 5.5 V; abs max -0.3 V to 7.5 V.
7 SW2CSN input SW2 current sense feedback (-ve), routed differentially with SW2CSP; abs max -0.3 V to 7.5 V.
8 SW2CSP input SW2 current sense feedback (+ve), routed differentially with SW2CSN; abs max -0.3 V to 7.5 V.
9 SW2GLS output SW2 low side MOSFET gate output, connect to the gate of the external low side MOSFET; abs max -0.3 V to 5.5 V.
10 SW2LX passive SW2 switching node and high side gate drive return path, routed parallel to SW2GHS trace; abs max -0.3 V to 40 V.
11 SW2GHS output SW2 high side MOSFET gate output, connect to the gate of the external high side MOSFET; abs max -0.3 V to (SW2BOOT + 0.3 V).
12 SW2BOOT passive SW2 bootstrap pin, connect bootstrap capacitor between SW2BOOT and SW2LX; abs max -0.3 V to VSW2LX + 6 V.
13 GPO3 output General-purpose output 3 (VMON4/GPIO3 pin, only GPO3 available in QM version); abs max -0.3 V to 5.5 V.
14 GPO2 output General-purpose output 2 (VMON3/GPIO2 pin, only GPO2 available in QM version); abs max -0.3 V to 5.5 V.
15 NA input Not available in QM version (VMON2 in other versions), connect to ground; abs max -0.3 V to 5.5 V.
16 NA input Not available in QM version (VMON1 in other versions), connect to ground; abs max -0.3 V to 10 V.
17 SW1BOOT passive SW1 bootstrap pin, connect bootstrap capacitor between SW1BOOT and SW1LX; abs max -0.3 V to VSW1LX + 6 V.
18 SW1IN power_in SW1 input voltage, bypass with at least 10 µF for both SW1IN pins together; abs max -0.3 V to 40 V.
19 SW1IN power_in SW1 input voltage, bypass with at least 10 µF for both SW1IN pins together; abs max -0.3 V to 40 V.
20 SW1LX power_out SW1 switching node, connect to inductor; abs max -0.3 V to 40 V.
21 SW1LX power_out SW1 switching node, connect to inductor; abs max -0.3 V to 40 V.
22 EN2 input SW2 enable input pin; abs max -0.3 V to 40 V.
23 EN1 input SW1 enable input pin; abs max -0.3 V to 40 V.
24 NA input Not available in QM version (FS0B in other versions), connect to ground; abs max -0.3 V to 40 V.
25 SW1FB input SW1 output voltage feedback, internal or external divider for outputs ≤ 5.5 V and external divider for outputs > 5.5 V; abs max -0.3 V to 7 V.
26 PGOOD1 output Open-drain PGOOD1 output from monitoring of selected voltage monitors; abs max -0.3 V to 5.5 V.
27 PGOOD2 output Open-drain PGOOD2 output from monitoring of selected voltage monitors; abs max -0.3 V to 5.5 V.
28 VDIG power_out Internal logic regulator output, bypass with 2.2 µF, no external loading permitted; abs max -0.3 V to 2.0 V.
29 BIAS_IN power_in External bias supply input (< 5.5 V), bypass with 1 µF; abs max -0.3 V to 5.5 V.
30 VCC power_out VCC regulator/switch output, nominally 4.7 V without BIAS_IN, bypass with 10 µF, no external loading permitted; abs max -0.3 V to 5.5 V.
31 MODE/SYNCIN input OTP-selectable external clock synchronization input or PFM/PWM mode select; abs max -0.3 V to 5.5 V.
32 VIN power_in Input to internal circuitry, connect to battery input; abs max -0.3 V to 40 V.
33 EPAD power_in Exposed pad, connect to ground with a sufficient number of thermal vias.

Key specifications

Parameter Value
Manufacturer NXP Semicon
Package HVQFN-32(5x5)
Category Power Management (PMIC)
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN Rising Threshold VIN_r 5.7 V minimum VIN for FS5600 to turn on 13
VIN and SW1/2IN recommended operating voltage VIN 2.7 36 V after crossing VIN_r, BIAS_IN = 5 V powers VCC 13
VIN and SW1/2IN recommended operating voltage VIN 4.4 36 V after crossing VIN_r, BIAS_IN = 0 V 13
SW1 Output Voltage Accuracy VSW1ACC -2 2 % PWM mode, SW1IN = 6 V to 18 V, 0 A <= ISW <= Rated A, minimum 2 V headroom, Vout = 1.8 V to 5.5 V using internal resistor divider 14
SW1 Output Voltage Accuracy in Dropout VSW1ACCDO -3 3 % PWM mode, SW1IN = 6 V to (Vout+2 V), 0 A <=ISW <= Rated A, 25C, Vout <= 5 V, 450 kHz 14
SW1 Reference accuracy with external resistor divider VSW1ACC 0.99 1 1.01 V external resistor divider 14
SW1 load current (PWM mode) VSW1LOAD 3 A PWM mode 14
SW1 operating frequency range SW1FSW 250 3000 kHz selectable via OTP 14
SW2 Output Voltage Accuracy VSW2ACC -3 3 % Vout = 1.8 V to 5.5 V, internal resistor divider, PWM mode, Not in dropout, Vin up to 36 V 22
SW2 Output Voltage Accuracy PFM VSW2ACC -3 3 % Internal resistor divider, PFM mode, Vin = 12 V, Load = 0 A to 10 mA 22
SW2 reference accuracy external divider SW2REF 0.98 1 1.02 V external resistor divider 22
SW2 current limit forward VSW2CSLIM 35 50 65 mV OTP_SW2_ILIM[1:0] = 00 22
SW2 current limit forward VSW2CSLIM 60 80 100 mV OTP_SW2_ILIM[1:0] = 01 22
SW2 current limit forward VSW2CSLIM 96 120 144 mV OTP_SW2_ILIM[1:0] = 10 22
SW2 current limit forward VSW2CSLIM 120 150 180 mV OTP_SW2_ILIM[1:0] = 11 22
SW2 current limit reverse VSW2CSLIM 35 50 65 mV Sense Resistor 10 mΩ to 20 mΩ, reverse direction 23
SW2 PWM switching frequency range fsw 300 2400 kHz Programmable via OTP 23
SW2 Error Amplifier Transconductance GM 1 1.5 2.3 mS COMP = 0.9 V 23
EN2 pin rising threshold EN2RTH 1.4 V 23
EN2 pin falling threshold EN2FTH 0.95 V 23
SW2 monitor over voltage threshold 5 15 % % of nominal 23
SW2 monitor under voltage threshold -15 -5 % % of nominal 23
High frequency clock accuracy F20 MHz 18.8 20 21.2 MHz 20 MHz setting 33
SYNCIN input falling threshold VIL_SYNCIN 0.35 V 33
SYNCIN input rising threshold VIH_SYNCIN 1.25 V 33
SYNCIN input clock frequency range FSYNCIN 2000 3000 kHz OTP_FSYNC_RANGE = 0 34
SYNCIN input clock frequency range FSYNCIN 333 500 kHz OTP_FSYNC_RANGE = 1 34
SYNCIN accepted duty cycle Fduty 40 60 % 34
SYNCOUT output logic level low VOL_SYNCOUT 0 0.3 V max printed as 0.3 x VDDIO 34
SYNCOUT output logic level high VOH_SYNCOUT 0.7 V min printed as 0.7 x VDDIO; max VDDIO 34
Thermal shutdown temperature TSD 155 165 175 °C 41
Ambient Operating Temperature Range (Automotive) TA -40 125 °C 12
Operating Junction Temperature Range TJ -40 150 °C 12
Peak package reflow temperature TPPRT 260 °C 12
Storage Temperature Range TST -55 150 °C 12
Junction to Ambient Thermal Resistance RθJA 36.3 °C/W JESD51-9, 2s2p 12
Junction to Ambient Thermal Resistance RθJA 31.7 °C/W Customized, 2s4p 12
Junction to Ambient Thermal Resistance RθJA 29.4 °C/W Customized, 2s6p 12
Junction-to-Top Thermal Characterization Parameter ΨJT 4.5 °C/W JESD51-9, 2s2p 12
Junction-to-Top Thermal Characterization Parameter ΨJT 4.4 °C/W Customized, 2s4p 12
Shutdown Mode quiescent current Iq4 7.5 µA 13
ESD HBM all pins VESD 2000 V printed ±2000 11
ESD CDM all pins VESD 500 V printed ±500 11

CAD (KiCad official)

  • Symbol: MFS5600AMMA0ES
  • Footprint: Package_DFN_QFN:HVQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm
  • 3D model: HVQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: mfs5600amma0es-etched.step / mfs5600amma0es-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mfs5600amma0es.step / mfs5600amma0es.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NXP Semicon datasheet (119 pp, sha256 6bddcefd253e1bc3, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF