# MF10CCWMX

**Texas Instruments** · Switched Capacitor Filters · SOIC-20-300mil

MF10CCWMX from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LP | output | Second-order lowpass output that can typically sink 1.5 mA and source 3 mA, and typically swings to within 1 V of each supply. |
| 2 | BP | output | Second-order bandpass output that can typically sink 1.5 mA and source 3 mA, and typically swings to within 1 V of each supply. |
| 3 | N/AP/HP | output | Configurable notch, allpass or highpass output that can typically sink 1.5 mA and source 3 mA, and typically swings to within 1 V of each supply. |
| 4 | INV | input | Inverting input of the summing op-amp; it is high impedance with the non-inverting input internally tied to AGND, so it acts as a low-impedance current summing junction. |
| 5 | S1 | input | Signal input for allpass configurations (modes 4 and 5) that should be driven with a source impedance below 1 kΩ, or tied to AGND if not driven. |
| 6 | SA/B | input | Switch control that connects one summer input to AGND when tied to V- or to the LP output when tied to V+. |
| 7 | VA+ | power_in | Analog positive supply, internally connected to VD+ through the substrate, so it should be derived from the same supply source and may be tied to VD+ and bypassed with a single capacitor. |
| 8 | VD+ | power_in | Digital positive supply, internally connected to VA+ through the substrate, so it should be derived from the same supply source and may be tied to VA+ and bypassed with a single capacitor. |
| 9 | LSh | input | Level shift pin for clock-level and supply configurations: tie to system ground for ±5V CMOS or 0 to +5V TTL clocks, and bias at +5V for CMOS clocks in 10V single-supply operation. |
| 10 | CLKA | input | Clock input for the first filter building block that should match the level of CLKB (TTL or CMOS) and have a duty cycle close to 50%, especially above 200 kHz. |
| 11 | CLKB | input | Clock input for the second filter building block that should match the level of CLKA (TTL or CMOS) and have a duty cycle close to 50%, especially above 200 kHz. |
| 12 | 50/100/CL | input | Tie high for a 50:1 clock-to-center-frequency ratio, mid-supply for 100:1, or low to trigger a current limit of about 2.5 mA that aborts filtering. |
| 13 | VD- | power_in | Digital negative supply, internally connected to VA- through the substrate, so it should be derived from the same supply source as VA-. |
| 14 | VA- | power_in | Analog negative supply, internally connected to VD- through the substrate, so it should be derived from the same supply source as VD-. |
| 15 | AGND | power_in | Analog ground that should be connected to system ground for dual supply or biased to mid-supply for single supply, and requires a clean ground for optimum filter performance. |
| 16 | S1 | input | Second signal input for allpass configurations (modes 4 and 5) that should be driven with a source impedance below 1 kΩ, or tied to AGND if not driven. |
| 17 | INV | input | Second inverting input of the summing op-amp; it is high impedance with the non-inverting input internally tied to AGND, so it acts as a low-impedance current summing junction. |
| 18 | N/AP/HP | output | Second configurable notch, allpass or highpass output that can typically sink 1.5 mA and source 3 mA, and typically swings to within 1 V of each supply. |
| 19 | BP | output | Second second-order bandpass output that can typically sink 1.5 mA and source 3 mA, and typically swings to within 1 V of each supply. |
| 20 | LP | output | Second second-order lowpass output that can typically sink 1.5 mA and source 3 mA, and typically swings to within 1 V of each supply. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Filters |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (V+ − V−) | V+ − V− | 9 |  | 14 | V |  | 3 |
| Maximum Supply Current | IS |  | 8 | 12 | mA | Clock applied to pins 10 & 11; no input signal | 3 |
| Center Frequency Range (min) | fO | 0.2 | 0.1 |  | Hz | fO × Q < 200 kHz | 3 |
| Center Frequency Range (max) | fO |  | 30 | 20 | kHz |  | 3 |
| Clock Frequency Range (min) | fCLK | 10 | 5 |  | Hz |  | 3 |
| Clock Frequency Range (max) | fCLK |  | 1.5 | 1 | MHz |  | 3 |
| Clock to Center Frequency Ratio Deviation (50:1) | fCLK/fO | -1.5 | 0.2 | 1.5 | % | Vpin12 = 5V; Q = 10, Mode 1; fCLK = 250 kHz | 3 |
| Clock to Center Frequency Ratio Deviation (100:1) | fCLK/fO | -1.5 | 0.2 | 1.5 | % | Vpin12 = 0V; Q = 10, Mode 1; fCLK = 500 kHz | 3 |
| Q Error (MAX) | Q Error (MAX) | -6 | 2 | 6 | % | Vpin12 = 5V; Q = 10, Mode 1; fCLK = 250 kHz | 3 |
| DC Lowpass Gain | HOLP | -0.2 | 0 | 0.2 | dB | Mode 1; R1 = R2 = 10k | 3 |
| DC Offset Voltage | VOS1 | -20 | 5 | 20 | mV |  | 3 |
| DC Offset Voltage | VOS2 | -185 | -150 | -85 | mV | Vpin12 = +5V; SA/B = V+; fCLK/fO = 50 | 3 |
| DC Offset Voltage | VOS3 | -100 | -70 | -20 | mV | Vpin12 = +5V; All Modes; fCLK/fO = 50 | 3 |
| Minimum Output Voltage Swing | VOUT | -3.8 | 4.25 | 3.8 | V | BP, LP pins; RL = 5k | 3 |
| CMOS Clock Input Voltage, Logical 1 |  | 3 |  |  | V | V+ = +5V, V− = −5V, VLSh = 0V | 4 |
| CMOS Clock Input Voltage, Logical 0 |  |  |  | -3 | V | V+ = +5V, V− = −5V, VLSh = 0V | 4 |
| CMOS Clock Input Voltage, Logical 1 |  | 8 |  |  | V | V+ = +10V, V− = 0V, VLSh = +5V | 4 |
| CMOS Clock Input Voltage, Logical 0 |  |  |  | 2 | V | V+ = +10V, V− = 0V, VLSh = +5V | 4 |
| TTL Clock Input Voltage, Logical 1 |  | 2 |  |  | V | V+ = +5V, V− = −5V, VLSh = 0V | 4 |
| TTL Clock Input Voltage, Logical 0 |  |  |  | 0.8 | V | V+ = +5V, V− = −5V, VLSh = 0V | 4 |
| Supply Voltage (V+ − V−) | V+ − V− |  |  | 14 | V |  | 2 |
| Input Current at Any Pin |  |  |  | 5 | mA | VIN < V− or VIN > V+ (footnote 3) | 2 |
| Package Input Current |  |  |  | 20 | mA |  | 2 |
| Power Dissipation |  |  |  | 500 | mW |  | 2 |
| Storage Temperature |  |  |  | 150 | °C |  | 2 |
| Soldering Temperature, Vapor Phase |  |  |  | 215 | °C | SO package, 60 s | 2 |
| Soldering Temperature, Infrared |  |  |  | 220 | °C | SO package, 15 s | 2 |
| Operating Temperature Range (TMIN to TMAX) | TA | 0 |  | 70 | °C | MF10CCWM | 3 |
| Junction-to-Ambient Thermal Resistance | θJA |  | 66 |  | °C/W | Board mounted, typical; MF10ACWM/CCWM | 2 |
| Maximum Junction Temperature | TJMAX |  |  | 125 | °C |  | 2 |

## CAD (KiCad official)

- Symbol: `MF10CCWMX`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `mf10ccwmx-etched.step` / `mf10ccwmx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mf10ccwmx.step` / `mf10ccwmx.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/mf10-n) (35 pp, sha256 `0e837564aa0bc5e6`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mf10ccwmx-datasheet.pdf)