component
me3118aspg
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MICRONE DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownME3118ASPG
MICRONE · DC-DC Converters · ESOP-8
ME3118ASPG from MICRONE, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground. Return path for the internal low-side NMOS power switch. Must be connected to AGND (recommended star-tie at a single point to avoid PGND noise coupling into AGND). |
| 2 | VIN | power_in | Power supply input, 4.5 V to 18 V (absolute max 20 V). The device starts operating when VIN is above the UVLO threshold (typ. 4.0 V rising / 3.6 V falling) and EN is high. Bypass with a low-ESR ceramic input capacitor placed close to this pin and PGND. |
| 3 | AGND | power_in | Analog ground and reference potential for the internal controller. Must be connected to PGND (single-point tie when a ground plane is not used). |
| 4 | FB | input | Feedback input to the internal error amplifier. Set the output voltage with a resistor divider from VOUT to AGND: VO = 0.8 V × (1 + R1/R2). Internal reference VFB = 0.8 V (788-812 mV); input bias current is 200 nA max. |
| 5 | COMP | output | External loop compensation node - output of the internal transconductance error amplifier. Connect a series RC network from COMP to AGND to place the compensation pole/zero pair. Internal clamp limits COMP swing to approximately 0.4 V to 2.5 V. |
| 6 | EN | input | Enable input. Drive high (≥2 V) to enable the regulator; drive low (≤0.6 V) to shut it down (IOFF ≈ 1 µA typ.). Input hysteresis ~200 mV; input current ≤1 µA. Do not float - tie to VIN if enable control is not needed. |
| 7 | SS | output | Soft-start pin. An internal 5 µA current source charges an external capacitor from SS to AGND, ramping the internal reference during startup to limit inrush current and provide a monotonic output rise. Typical soft-start time is ~3 ms. |
| 8 | NC | unconnected | No internal connection. Leave floating or tie to ground for best PCB layout; do not use as a routing via. |
| 9 | LX | power_out | Switch node - exposed thermal pad on the ESOP-8. Internally the common drain of the high-side PMOS and low-side NMOS power switches; connect to the external filter inductor. Also serves as the primary thermal dissipation path - solder to a large copper area to lower θJA. Absolute max: −0.7 V to VIN+0.3 V DC (−5 V to 22 V for 20 ns transients). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MICRONE |
| Package | ESOP-8 |
| Category | PMIC |
| Pins | 9 |
Ordering variants
ME3118ASPG
CAD (KiCad official)
- Symbol:
ME3118ASPG - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
me3118aspg-etched.step/me3118aspg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);me3118aspg.step/me3118aspg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MICRONE datasheet (None pp, sha256
d7aa79dda3b2a9e4, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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