MDT40N10D

Minos · MOSFETs · TO-252

MDT40N10D from Minos, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	G	input	Gate; the pin on the left of the TO-252 package drawing, with a gate-source voltage limit of ±20V and a threshold of 2V min to 4V max at ID=250μA.
2	D	passive	Drain; the middle lead, which is shorter and shares the drain with the exposed tab. It is rated for VDS=100V and ID=33A continuous (100A pulsed).
3	S	passive	Source; the pin on the right of the TO-252 package drawing, which carries the load current up to 33A continuous.

Key specifications

Parameter	Value
Manufacturer	Minos
Package	TO-252
Category	Transistors/Thyristors
Pins	3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Drain-Source Voltage	VDS			100	V		1
Gate-Source Voltage	VGS	-20		20	V		1
Drain Current-Continuous	ID			33	A		1
Drain Current-Pulsed	IDM			100	A	Note 1: pulse width limited by maximum junction temperature	1
Maximum Power Dissipation	PD			70	W	Tc=25℃	1
Single pulse avalanche energy	EAS			96	mJ	Note 2: Tj=25℃, VDD=50V, VGS=10V, L=0.5mH, Rg=25Ω	1
Operating Junction and Storage Temperature Range	TJ,TSTG	-55		175	℃		1
Thermal Resistance, Junction-to-Case	RθJC			3.5	℃/W		1
Drain-Source Breakdown Voltage	BVDSS	100			V	VGS=0V ID=250μA	2
Zero Gate Voltage Drain Current	IDSS			1	μA	VDS=100V,VGS=0V	2
Gate-Body Leakage Current	IGSS	-100		100	nA	VGS=±20V,VDS=0V	2
Gate Threshold Voltage	VGS(th)	2	3	4	V	VDS=VGS,ID=250μA	2
Drain-Source On-State Resistance	RDS(ON)		22	26	mΩ	VGS=10V, ID=12A; Note 3 pulse test	2
Turn-Off Fall Time	tf	13.4			nS	VDD=50V, ID=20A, VGS=10V, RGEN=10Ω	2
Diode Forward Voltage	VSD			1.2	V	VGS=0V,IS=20A	2

CAD (KiCad official)

Symbol: MDT40N10D
Footprint: Package_TO_SOT_SMD:TO-252-2
3D model: TO-252 (KiCad packages3D, STEP)
3D model files: mdt40n10d-etched.step / mdt40n10d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mdt40n10d.step / mdt40n10d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Minos datasheet (7 pp, sha256 b903ef14be5f195f, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# MDT40N10D

**Minos** · MOSFETs · TO-252

MDT40N10D from Minos, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate; the pin on the left of the TO-252 package drawing, with a gate-source voltage limit of ±20V and a threshold of 2V min to 4V max at ID=250μA. |
| 2 | D | passive | Drain; the middle lead, which is shorter and shares the drain with the exposed tab. It is rated for VDS=100V and ID=33A continuous (100A pulsed). |
| 3 | S | passive | Source; the pin on the right of the TO-252 package drawing, which carries the load current up to 33A continuous. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Minos |
| Package | TO-252 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS |  |  | 100 | V |  | 1 |
| Gate-Source Voltage | VGS | -20 |  | 20 | V |  | 1 |
| Drain Current-Continuous | ID |  |  | 33 | A |  | 1 |
| Drain Current-Pulsed | IDM |  |  | 100 | A | Note 1: pulse width limited by maximum junction temperature | 1 |
| Maximum Power Dissipation | PD |  |  | 70 | W | Tc=25℃ | 1 |
| Single pulse avalanche energy | EAS |  |  | 96 | mJ | Note 2: Tj=25℃, VDD=50V, VGS=10V, L=0.5mH, Rg=25Ω | 1 |
| Operating Junction and Storage Temperature Range | TJ,TSTG | -55 |  | 175 | ℃ |  | 1 |
| Thermal Resistance, Junction-to-Case | RθJC |  |  | 3.5 | ℃/W |  | 1 |
| Drain-Source Breakdown Voltage | BVDSS | 100 |  |  | V | VGS=0V ID=250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 1 | μA | VDS=100V,VGS=0V | 2 |
| Gate-Body Leakage Current | IGSS | -100 |  | 100 | nA | VGS=±20V,VDS=0V | 2 |
| Gate Threshold Voltage | VGS(th) | 2 | 3 | 4 | V | VDS=VGS,ID=250μA | 2 |
| Drain-Source On-State Resistance | RDS(ON) |  | 22 | 26 | mΩ | VGS=10V, ID=12A; Note 3 pulse test | 2 |
| Turn-Off Fall Time | tf | 13.4 |  |  | nS | VDD=50V, ID=20A, VGS=10V, RGEN=10Ω | 2 |
| Diode Forward Voltage | VSD |  |  | 1.2 | V | VGS=0V,IS=20A | 2 |

## CAD (KiCad official)

- Symbol: `MDT40N10D`
- Footprint: `Package_TO_SOT_SMD:TO-252-2`
- 3D model: TO-252 (KiCad packages3D, STEP)
- 3D model files: `mdt40n10d-etched.step` / `mdt40n10d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mdt40n10d.step` / `mdt40n10d.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Minos datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590917980094623744) (7 pp, sha256 `b903ef14be5f195f`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mdt40n10d-datasheet.pdf)