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MCP73871-2AAI

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Microchip Tech Battery Management ICs, QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MCP73871-2AAI

Microchip Tech · Battery Management ICs · QFN-20-EP(4x4)

MCP73871-2AAI from Microchip Tech, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out System output terminal that powers the system load while the battery charges independently; bypass to VSS with a minimum of 4.7 µF.
2 VPCC input Voltage proportional charge control input; supply 1.23V or greater to enable, or connect to IN to disable the feature.
3 SEL input Input type selection: Low for USB port, High for AC-DC adapter.
4 PROG2 input USB port input current limit selection when SEL = Low (Low = 100 mA, High = 500 mA).
5 THERM bidirectional Thermistor monitoring input and bias current for battery cell temperature monitoring.
6 PG output Open-drain Power-Good status output, low when the input is above the UVLO threshold and greater than the battery voltage.
7 STAT2 output Open-drain charge status output 2 for driving an LED or a pull-up to a host microcontroller.
8 STAT1/LBO output Open-drain charge status output 1, also low battery output indicator when VBAT > VIN.
9 TE input Timer enable; enables the safety timer when active Low.
10 VSS power_in Battery management 0V reference; connect to negative terminal of the battery, system load and input supply.
11 VSS power_in Battery management 0V reference; connect to negative terminal of the battery, system load and input supply.
12 PROG3 bidirectional Termination set point for both AC-DC adapter and USB port.
13 PROG1 bidirectional Fast charge current regulation setting (resistor to VSS) with SEL = High, and preconditioning set point for both USB port and AC-DC adapter.
14 VBAT power_in Battery positive input and output connection; bypass to VSS with a minimum of 4.7 µF.
15 VBAT power_in Battery positive input and output connection; bypass to VSS with a minimum of 4.7 µF.
16 VBAT_SENSE bidirectional Battery voltage sense; connect to battery positive terminal, final voltage regulated to VREG.
17 CE input Device charge enable; enabled when CE = High.
18 IN power_in Power supply input; VREG + 0.3V to 6V recommended, bypass to VSS with a minimum of 4.7 µF.
19 IN power_in Power supply input; VREG + 0.3V to 6V recommended, bypass to VSS with a minimum of 4.7 µF.
20 OUT power_out System output terminal that powers the system load while the battery charges independently; bypass to VSS with a minimum of 4.7 µF.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-20-EP(4x4)
Category Power Management ICs
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VIN 6 V min is VREG + 0.3V 5
Supply Current - Charging ISS 2500 3750 μA Charging 5
Supply Current - Charge Complete ISS 260 350 μA Charge Complete 5
Supply Current - Standby ISS 180 300 μA Standby 5
Supply Current - Shutdown ISS 28 50 μA Shutdown (VDD < VBAT, 100 mV or VDD < VSTOP) 5
Regulated Charge Voltage (4.20V option) VREG 4.179 4.2 4.221 V VDD = [VREG(typical) + 1V], IOUT = 10 mA, TA = -5°C to +55°C 5
Regulated Charge Voltage Tolerance VRTOL -0.5 0.5 % TA = +25°C 5
Regulated Charge Voltage Tolerance VRTOL -0.75 0.75 % TA = -5°C to +55°C 5
Line Regulation ΔVBAT/VBAT/ΔVDD 0.08 0.2 %/V VDD = [VREG(typical) + 1V] to 6V, IOUT = 10 mA 5
Load Regulation ΔVBAT/VBAT 0.08 0.18 % IOUT = 10 mA to 150 mA, VDD = [VREG(typical) + 1V] 5
AC-Adapter Fast Charge Current IREG 90 100 110 mA PROG1 = 10 k, TA = -5°C to +55°C, SEL = Hi 6
AC-Adapter Fast Charge Current IREG 900 1000 1100 mA PROG1 = 1 k, TA = -5°C to +55°C, SEL = Hi 6
USB Fast Charge Current IREG 80 90 100 mA PROG2 = Low, SEL = Low, (Note 2), TA = -5°C to +55°C 6
USB Fast Charge Current IREG 400 450 500 mA PROG2 = High, SEL = Low, (Note 2), TA = -5°C to +55°C 6
USB-Port Supply Current Limit ILIMIT_USB 80 90 100 mA PROG2 = Low, SEL = Low, TA = -5°C to +55°C 6
USB-Port Supply Current Limit ILIMIT_USB 400 450 500 mA PROG2 = High, SEL = Low, TA = -5°C to +55°C 6
AC-DC Adapter Current Limit ILIMIT_AC 1500 1650 1800 mA SEL = High, TA = -5°C to +55°C 6
VPCC Input Threshold Tolerance VRTOL -3 3 % 6
VPCC Input Leakage Current ILK 0.01 1 μA VVPCC = VDD 6
Precondition Current Ratio IPREG/IREG 7.5 10 12.5 % PROG1 = 1.0 k to 10 k, TA = -5°C to +55°C 6
Precondition Current Threshold Ratio VPTH/VREG 69 72 75 % VBAT Low-to-High 6
Charge Termination Current ITERM 75 100 125 mA PROG3 = 10 k, TA = -5°C to +55°C 6
Charge Termination Current ITERM 7.5 10 12.5 mA PROG3 = 100 k, TA = -5°C to +55°C 6
Output Reverse Leakage Current - Shutdown IDISCHARGE 30 40 μA Shutdown (VBAT < VDD < VUVLO) 7
Output Reverse Leakage Current - No Load IDISCHARGE 30 40 μA VBAT = Power Out, No Load 7
Output Reverse Leakage Current - Charge Complete IDISCHARGE -6 -13 μA Charge Complete 7
Status Indicator Sink Current ISINK 16 35 mA 7
Status Indicator Low Output Voltage VOL 0.4 1 V ISINK = 4 mA 7
Status Indicator Input Leakage Current ILK 0.01 1 μA High Impedance, VDD on pin 7
PROG1 Charge Impedance Range RPROG 1 20 kΩ 7
PROG3 Termination Impedance Range RPROG 5 100 kΩ 7
PROG2 Input High Voltage Level VIH 1.8 V 7
PROG2 Input Low Voltage Level VIL 0.8 V 7
PROG2 Input Leakage Current ILK 0.01 1 μA VPROG2 = VDD 7
TE Input High Voltage Level VIH 1.8 V Note 1 7
TE Input Low Voltage Level VIL 0.8 V Note 1 7
TE Input Leakage Current ILK 0.01 1 μA VTE = VDD 7
CE Input High Voltage Level VIH 1.8 V 8
CE Input Low Voltage Level VIL 0.8 V 8
CE Input Leakage Current ILK 0.01 1 μA VCE = VDD 8
SEL Input High Voltage Level VIH 1.8 V 8
SEL Input Low Voltage Level VIL 0.8 V 8
SEL Input Leakage Current ILK 0.01 1 μA VSEL = VDD 8
Thermistor Current Source ITHERM 47 50 53 μA 2 k < RTHERM < 50 k 8
Thermistor Upper Trip Threshold VT1 1.2 1.24 1.26 V VT1 Low-to-High 8
Thermistor Lower Trip Threshold VT2 0.23 0.25 0.27 V VT2 High-to-Low 8
UVLO Start Delay tSTART 5 ms VDD Low-to-High 9
Transition Time Out of Precondition tDELAY 10 ms VBAT < VPTH to VBAT > VPTH 9
Current Rise Time Out of Precondition tRISE 10 ms IOUT Rising to 90% of IREG 9
Precondition Comparator Filter Time tPRECON 0.4 1.3 3.2 ms Average VBAT Rise/Fall 9
Termination Comparator Filter Time tTERM 0.4 1.3 3.2 ms Average IOUT Falling 9
Charge Comparator Filter Time tCHARGE 0.4 1.3 3.2 ms Average VBAT Falling 9
Thermistor Comparator Filter Time tTHERM 0.4 1.3 3.2 ms Average THERM Rise/Fall 9
Status Output Turn-off tOFF 500 μs ISINK = 1 mA to 0 mA 9
Status Output Turn-on tON 500 μs ISINK = 0 mA to 1 mA 9
Specified Temperature Range TA -40 85 °C 9
Operating Temperature Range TJ -40 125 °C 9
Input Voltage VIN 7 V 5
Storage Temperature -65 150 °C 5
Thermal Resistance Junction-to-Ambient, 20LD-QFN 4x4 θJA 50 °C/W 4-Layer JC51-7 Standard Board, Natural Convection 9
Thermal Shutdown Die Temperature TSD 150 °C 8

CAD (KiCad official)

  • Symbol: MCP73871-2AAI
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: mcp73871-2aai-etched.step / mcp73871-2aai-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp73871-2aai.step / mcp73871-2aai.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (40 pp, sha256 bc4dc7e5bca1f6a2, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF