component
MCP73833T-FCI
Public Made by Adomby adom
Microchip Tech Battery Management, DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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MCP73833T-FCI
Microchip Tech · Battery Management · DFN-10-EP(3x3)
MCP73833T-FCI from Microchip Tech, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Battery management input supply; a supply of [VREG (typical) + 0.3V] to 6V is recommended, bypassed to VSS with a minimum of 1 µF. |
| 2 | VDD | power_in | Battery management input supply; a supply of [VREG (typical) + 0.3V] to 6V is recommended, bypassed to VSS with a minimum of 1 µF. |
| 3 | STAT1 | output | Open-drain charge status output for an LED or a pull-up resistor to a host microcontroller. |
| 4 | STAT2 | output | Open-drain charge status output for an LED or a pull-up resistor to a host microcontroller. |
| 5 | VSS | power_in | Battery management 0V reference; connect to the negative terminal of the battery and the input supply. |
| 6 | PROG | passive | Current regulation set: a resistor from PROG to VSS scales the preconditioning, fast charge and termination currents, and floating PROG disables the charge controller. |
| 7 | PG | output | Power good pseudo open-drain output (MCP73833 option) that can sink but not source current, is low when the input is above UVLO and greater than the battery voltage, and should only be pulled up to the input. |
| 8 | THERM | input | Thermistor input biased by an internal 50 µA current source for a 10 kΩ NTC; compared to factory thresholds of 1.20V and 0.25V (typical). |
| 9 | VBAT | power_out | Battery charge control output connected to the positive battery terminal, drain of the internal P-channel pass transistor, bypassed to VSS with a minimum of 1 µF for loop stability. |
| 10 | VBAT | power_out | Battery charge control output connected to the positive battery terminal, drain of the internal P-channel pass transistor, bypassed to VSS with a minimum of 1 µF for loop stability. |
| 11 | EP | passive | Exposed thermal pad with an internal connection to VSS; it must be connected to the same potential as VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | DFN-10-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (charging) | VDD | 3.75 | 6 | V | Charging | 3 | |
| Supply Voltage (charge complete, standby) | VDD | 6 | V | Charge Complete, Standby | 3 | ||
| Supply Current (charging) | ISS | 2000 | 3000 | µA | Charging | 3 | |
| Supply Current (charge complete) | ISS | 150 | 300 | µA | Charge Complete | 3 | |
| Supply Current (standby) | ISS | 100 | 300 | µA | Standby (No Battery or PROG Floating) | 3 | |
| Supply Current (shutdown) | ISS | 50 | 100 | µA | Shutdown (VDD < VBAT, or VDD < VSTOP) | 3 | |
| UVLO Start Threshold | VSTART | 3.4 | 3.55 | 3.7 | V | VDD Low-to-High | 3 |
| UVLO Stop Threshold | VSTOP | 3.3 | 3.45 | 3.6 | V | VDD High-to-Low | 3 |
| Line Regulation | /(ΔVBAT/VBAT)/ΔVDD/ | 0.1 | 0.3 | %/V | VDD=[VREG(Typical)+1V] to 6V, IOUT=10 mA | 3 | |
| Load Regulation | /ΔVBAT/ VBAT/ | 0.1 | 0.3 | % | IOUT=10 mA to 100 mA, VDD=[VREG(Typical)+1V] | 3 | |
| Fast Charge Current Regulation | IREG | 90 | 100 | 110 | mA | PROG = 10 kΩ | 3 |
| Fast Charge Current Regulation | IREG | 900 | 1000 | 1100 | mA | PROG = 1.0 kΩ | 3 |
| Status Indicator Sink Current | ISINK | 15 | 25 | mA | 4 | ||
| Status Indicator Low Output Voltage | VOL | 0.4 | 1 | V | ISINK = 4 mA | 4 | |
| Status Indicator Input Leakage Current | ILK | 0.01 | 1 | µA | High Impedance, 6V on pin | 4 | |
| Charge Impedance Range | RPROG | 1 | 20 | kΩ | 4 | ||
| Standby Impedance | RPROG | 70 | 200 | kΩ | Minimum Impedance for Standby | 4 | |
| Thermistor Current Source | ITHERM | 47 | 50 | 53 | µA | 2 kΩ < RTHERM < 50 kΩ | 4 |
| Upper Trip Threshold | VT1 | 1.2 | 1.23 | 1.26 | V | VTHERM Low-to-High | 4 |
| Lower Trip Threshold | VT2 | 0.235 | 0.25 | 0.265 | V | VTHERM High-to-Low | 4 |
| THERM Input Sink Current | ISINK | 3 | 6 | 20 | µA | Stand-by or system test mode | 4 |
| Bypass Capacitance | CBAT | 1 | µF | IOUT < 250 mA | 4 | ||
| Bypass Capacitance | CBAT | 4.7 | µF | IOUT > 250 mA | 4 | ||
| Output Reverse Leakage Current | IDISCHARGE | 0.15 | 2 | µA | PROG Floating | 4 | |
| Output Reverse Leakage Current | IDISCHARGE | 0.25 | 2 | µA | VDD < VBAT | 4 | |
| Output Reverse Leakage Current | IDISCHARGE | -5.5 | -15 | µA | Charge Complete | 4 | |
| Timer Enable Input High Voltage Level | VIH | 2 | V | 5 | |||
| Timer Enable Input Low Voltage Level | VIL | 0.6 | V | 5 | |||
| Timer Enable Input Leakage Current | ILK | 0.01 | 1 | µA | VTE = 6V | 5 | |
| UVLO Start Delay | tSTART | 5 | ms | VDD Low-to-High | 5 | ||
| Transition Time Out of Preconditioning | tDELAY | 1 | ms | VBATVPTH | 5 | ||
| Current Rise Time Out of Preconditioning | tRISE | 1 | ms | IOUT Rising to 90% of IREG | 5 | ||
| Preconditioning Comparator Filter Time | tPRECON | 0.4 | 1.3 | 3.2 | ms | Average VBAT Rise/Fall | 5 |
| Termination Comparator Filter Time | tTERM | 0.4 | 1.3 | 3.2 | ms | Average IOUT Falling | 5 |
| Charge Comparator Filter Time | tCHARGE | 0.4 | 1.3 | 3.2 | ms | Average VBAT Falling | 5 |
| Thermistor Comparator Filter Time | tTHERM | 0.4 | 1.3 | 3.2 | ms | Average THERM Rise/Fall | 5 |
| Status Output turn-off time | tOFF | 200 | µs | ISINK = 1 mA to 0 mA | 5 | ||
| Status Output turn-on time | tON | 200 | µs | ISINK = 0 mA to 1 mA | 5 | ||
| Specified Temperature Range | TA | -40 | 85 | °C | 5 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | 5 | ||
| Storage Temperature Range | TA | -65 | 150 | °C | 5 | ||
| Thermal Resistance, DFN-10 3 mm x 3 mm | θJA | 41 | °C/W | 4-Layer JC51-7 Standard Board, Natural Convection | 5 | ||
| Supply Voltage (absolute maximum) | VDD | 7 | V | 3 | |||
| ESD Protection, Human Body Model | 4 | kV | HBM (1.5 kΩ in series with 100 pF) | 3 | |||
| All Inputs and Outputs voltage | -0.3 | V | w.r.t. VSS | 3 |
CAD (KiCad official)
- Symbol:
MCP73833T-FCI - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
mcp73833t-fci-etched.step/mcp73833t-fci-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp73833t-fci.step/mcp73833t-fci.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (32 pp, sha256
887900adff279d0f, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).