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MCP73831T-5ACI

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Microchip Tech Battery Management, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MCP73831T-5ACI

Microchip Tech · Battery Management · SOT-23-5

MCP73831T-5ACI from Microchip Tech, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 STAT tri_state Charge status output for an LED or a pull-up resistor to a host microcontroller, and it is a tri-state logic output on the MCP73831 (open-drain on the MCP73832).
2 VSS power_in Battery management 0V reference that connects to the negative battery terminal and the input supply.
3 VBAT power_out Battery charge control output connected to the positive battery terminal and the drain of the internal P-channel pass transistor, which must be bypassed to VSS with a minimum of 4.7 µF for loop stability when the battery is disconnected.
4 VDD power_in Battery management input supply, recommended at [VREG (typical) + 0.3V] to 6V and bypassed to VSS with a minimum of 4.7 µF.
5 PROG input Current regulation set input where a resistor to VSS scales the preconditioning, fast-charge and termination currents and enables the device, while floating or a logic-high input disables the charge controller.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD 3.75 6 V 3
Supply Current (Charging) ISS 510 1500 µA Charging 3
Supply Current (Charge Complete, No Battery) 53 200 µA Charge Complete, No Battery 3
Supply Current (PROG Floating) 25 50 µA PROG Floating 3
Supply Current (Low-VDD Shutdown Band) 1 5 µA VDD < (VBAT - 50 mV) 3
Supply Current (Below UVLO) 0.1 2 µA VDD < VSTOP 3
UVLO Start Threshold VSTART 3.3 3.45 3.6 V VDD Low-to-High 3
UVLO Stop Threshold VSTOP 3.2 3.38 3.5 V VDD High-to-Low 3
Regulated Output Voltage (MCP7383X-5, 4.50 V) VREG 4.466 4.5 4.534 V VDD = [VREG(typical)+1V], IOUT = 10 mA, TA = -5°C to +55°C 3
Line Regulation 0.09 0.3 %/V VDD = [VREG(typical)+1V] to 6V, IOUT = 10 mA 3
Load Regulation 0.05 0.3 % IOUT = 10 mA to 50 mA, VDD = [VREG(typical)+1V] 3
Fast Charge Current Regulation (PROG = 10 k) IREG 90 100 110 mA PROG = 10 k 3
Fast Charge Current Regulation (PROG = 2.0 k) IREG 450 505 550 mA PROG = 2.0 k; Note 1 (not production tested) 3
Fast Charge Current Regulation (PROG = 67 k) IREG 12.5 14.5 16.5 mA PROG = 67 k 3
Precondition Current Ratio (Option AC, 10%) IPREG / IREG 7.5 10 12.5 % PROG = 2.0 k to 10 k 4
Precondition Voltage Threshold Ratio (Option AC, 66.5%) VPTH / VREG 64 66.5 69 % VBAT Low-to-High 4
Charge Termination Current Ratio (Option AC, 7.5%) ITERM / IREG 5.6 7.5 9.4 % PROG = 2.0 k to 10 k 4
Recharge Voltage Threshold Ratio (Option AC, 96.5%) VRTH / VREG 94 96.5 99 % VBAT High-to-Low 4
Battery Detection Current IBAT_DET 0.6 6 µA VBAT Source Current 4
No-Battery-Present Impedance ZNO_BAT 7 M VBAT Impedance ≥ ZNO_BAT for No Battery condition, Note 1 4
Output Reverse Leakage Current (PROG Floating) IDISCHARGE 0.15 2 µA PROG Floating 4
Output Reverse Leakage Current (VDD Floating) IDISCHARGE 0.25 2 µA VDD Floating 4
Output Reverse Leakage Current (VDD < VSTOP) IDISCHARGE 0.15 2 µA VDD < VSTOP 4
Output Reverse Leakage Current (Charge Complete) IDISCHARGE -5.5 -15 µA Charge Complete 4
STAT Sink Current ISINK 25 mA 4
STAT Low Output Voltage VOL 0.4 1 V ISINK = 4 mA 4
STAT Source Current ISOURCE 35 mA 4
STAT Input Leakage Current ILK 0.03 1 µA High-Impedance 4
PROG Charge Impedance Range RPROG 2 67 k 4
PROG Minimum Shutdown Impedance RPROG 70 200 k 4
UVLO Start Delay tSTART 5 ms VDD Low-to-High 5
Transition Time Out of Preconditioning tDELAY 1 ms VBAT < VPTH to VBAT > VPTH 5
Current Rise Time Out of Preconditioning tRISE 1 ms IOUT Rising to 90% of IREG 5
Termination Comparator Filter tTERM 0.4 1.3 3.2 ms Average IOUT Falling 5
Charge Comparator Filter tCHARGE 0.4 1.3 3.2 ms Average VBAT 5
Status Output Turn-Off Time tOFF 200 µs ISINK = 1 mA to 0 mA 5
Status Output Turn-On Time tON 200 µs ISINK = 0 mA to 1 mA 5
Specified Temperature Range TA -40 85 °C 5
Operating Temperature Range TJ -40 125 °C 5
Storage Temperature Range TA -65 150 °C 5
Thermal Resistance, Junction to Ambient (5-Lead SOT-23) JA 230 °C/W 4-Layer JC51-7 Standard Board, Natural Convection 5
Absolute Maximum VDD VDD 7 V 3
All Inputs and Outputs w.r.t. VSS (minimum) -0.3 V Maximum printed as (VDD+0.3) V, not entered 3
ESD Human Body Model 4 kV Human Body Model (1.5 k in Series with 100 pF) 3

CAD (KiCad official)

  • Symbol: MCP73831T-5ACI
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: mcp73831t-5aci-etched.step / mcp73831t-5aci-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp73831t-5aci.step / mcp73831t-5aci.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (29 pp, sha256 75297f2a52355993, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF