component
MCP6S22-I
Public Made by Adomby adom
Microchip Tech Operational Amplifier, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 7d ago |
| viewers | 7d ago |
| mcp6s22-i-etched.glb | 7d ago |
| mcp6s22-i-etched.step | 7d ago |
| mcp6s22-i-hero.glb | 7d ago |
| mcp6s22-i-hero.overlay.json | 7d ago |
| mcp6s22-i.glb | 7d ago |
| mcp6s22-i.kicad_mod | 7d ago |
| mcp6s22-i.kicad_sym | 7d ago |
| mcp6s22-i.lbr | 7d ago |
| mcp6s22-i.step | 7d ago |
| package.json | 7d ago |
| page.json | 7d ago |
| README.md | 7d ago |
| verification.json | 7d ago |
MCP6S22-I
Microchip Tech · Operational Amplifier · DIP-8
MCP6S22-I from Microchip Tech, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Analog output is a low-impedance voltage source whose value is set by the selected gain, the selected input and the voltage at VREF, and all inputs and outputs must stay between VSS - 0.3V and VDD + 0.3V (absolute maximum). |
| 2 | CH0 | input | Analog input CH0 is a high-impedance CMOS input with low bias current, and the input voltage range is VSS - 0.3V to VDD + 0.3V. |
| 3 | CH1 | input | Analog input CH1 is a high-impedance CMOS input with low bias current, and the input voltage range is VSS - 0.3V to VDD + 0.3V. |
| 4 | VSS | power_in | Negative power supply pin; in typical single-supply use it is connected to ground, and VDD must be 2.5V to 5.5V higher than VSS. |
| 5 | CS | input | SPI chip select is a Schmitt-triggered CMOS logic input. |
| 6 | SI | input | SPI serial data input is a Schmitt-triggered CMOS logic input. |
| 7 | SCK | input | SPI serial clock input is a Schmitt-triggered CMOS logic input. |
| 8 | VDD | power_in | Positive power supply pin, 2.5V to 5.5V above VSS, which needs a local 0.1 µF bypass capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | DIP-8 |
| Category | Operational Amplifier/Comparator |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | VOS | -275 | 275 | µV | G = +1, VDD = 4.0V | 2 | |
| Input Bias Current over Temperature | IB | 250 | pA | TA = -40 to +85°C, CHx = VDD/2 | 2 | ||
| Power Supply Rejection Ratio | PSRR | 70 | 85 | dB | G = +1 (Note 1) | 2 | |
| DC Gain Error, G = +1 | gE | -0.1 | 0.1 | % | VOUT 0.3V to VDD-0.3V | 2 | |
| DC Gain Error, G ≥ +2 | gE | -1 | 1 | % | VOUT 0.3V to VDD-0.3V | 2 | |
| Internal Resistance | RLAD | 3.4 | 4.9 | 6.4 | kΩ | (Note 1) | 2 |
| Supply Voltage | VDD | 2.5 | 5.5 | V | 3 | ||
| Quiescent Current | IQ | 0.5 | 1 | 1.35 | mA | IO = 0 (Note 2) | 3 |
| Quiescent Current, Shutdown mode | IQ_SHDN | 0.5 | 1 | µA | IO = 0 (Note 2) | 3 | |
| POR Trip Voltage | VPOR | 1.2 | 1.7 | 2.2 | V | (Note 3) | 3 |
| Input Leakage Current (CS, SI, SCK) | IIL | -1 | 1 | µA | 4 | ||
| Amplifier Output Leakage Current | -1 | 1 | µA | In Shutdown mode | 4 | ||
| Logic Threshold, Low (CS, SI, SCK) | VIL | 0 | V | 4 | |||
| Input Rise/Fall Times (CS, SI, SCK) | tRFI | 2 | µs | Note 1 | 4 | ||
| CS high time | tCSH | 40 | ns | 4 | |||
| SCK edge to CS fall setup time | tCS0 | 10 | ns | SCK edge when CS is high | 4 | ||
| CS fall to first SCK edge setup time | tCSSC | 40 | ns | 4 | |||
| SCK Frequency | fSCK | 10 | MHz | VDD = 5V (Note 2) | 4 | ||
| SCK high time | tHI | 40 | ns | 4 | |||
| SCK low time | tLO | 40 | ns | 4 | |||
| SCK last edge to CS rise setup time | tSCCS | 30 | ns | 4 | |||
| CS rise to SCK edge setup time | tCS1 | 100 | ns | SCK edge when CS is high | 4 | ||
| SI set-up time | tSU | 40 | ns | 4 | |||
| SI hold time | tHD | 10 | ns | 4 | |||
| Out of Shutdown mode (CS goes high) to Amplifier Output Turn-on Time | tON | 3.5 | 10 | µs | CS = 0.7VDD to VOUT 90% point | 4 | |
| Specified Temperature Range | TA | -40 | 85 | °C | 5 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | (Note 1) | 5 | |
| Storage Temperature Range | TA | -65 | 150 | °C | 5 | ||
| Supply voltage VDD - VSS | VDD - VSS | 7 | V | 2 | |||
| Current at Input Pin | 2 | mA | 2 | ||||
| Current at Output and Supply Pins | 30 | mA | 2 | ||||
| Storage temperature | -65 | 150 | °C | 2 | |||
| Junction temperature | 150 | °C | 2 | ||||
| ESD protection on all pins (HBM) | 2 | kV | 2 | ||||
| ESD protection on all pins (MM) | 200 | V | 2 | ||||
| Thermal Resistance, 8L-PDIP | JA | 85 | °C/W | 5 | |||
| Thermal Resistance, 8L-SOIC | JA | 163 | °C/W | 5 | |||
| Thermal Resistance, 8L-MSOP | JA | 206 | °C/W | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 8-Lead Plastic Small Outline (SN), Narrow, 150 mil (SOIC) Foot Angle 048048 | 32 |
CAD (KiCad official)
- Symbol:
MCP6S22-I - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
mcp6s22-i-etched.step/mcp6s22-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp6s22-i.step/mcp6s22-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (42 pp, sha256
d1ca1d52d76835f9, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).