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MCP6S21-I
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Microchip Tech Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP6S21-I
Microchip Tech · Operational Amplifier · SOIC-8
MCP6S21-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Analog output, a low-impedance voltage source whose value is set by the selected gain, the selected input and the VREF voltage. |
| 2 | CH0 | input | Analog input (the only channel on the MCP6S21), a high-impedance, low-bias-current CMOS input that can range from VSS-0.3V to VDD+0.3V. |
| 3 | VREF | power_in | External reference voltage pin, which should be between VSS and VDD and shifts the output voltage. |
| 4 | VSS | power_in | Negative supply, normally grounded in single-supply use. |
| 5 | CS | input | SPI chip select, a Schmitt-trigger CMOS logic input; taking it low starts communication and raising it executes the command. |
| 6 | SI | input | SPI serial data input, a Schmitt-trigger CMOS logic input clocked in on the rising edge of SCK. |
| 7 | SCK | input | SPI clock input, a Schmitt-trigger CMOS logic input with a maximum frequency of 10 MHz at VDD = 5V. |
| 8 | VDD | power_in | Positive supply, 2.5V to 5.5V above VSS, with a 0.1 µF bypass capacitor placed close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Amplifiers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | VOS | -275 | 275 | µV | G = +1, VDD = 4.0V | 2 | |
| Power Supply Rejection Ratio | PSRR | 70 | 85 | dB | G = +1 | 2 | |
| Input Bias Current over temperature | IB | 250 | pA | TA = -40 to +85°C, CHx = VDD/2 | 2 | ||
| DC Gain Error G = +1 | gE | -0.1 | 0.1 | % | VOUT ≈ 0.3V to VDD − 0.3V | 2 | |
| DC Gain Error G ≥ +2 | gE | -1 | 1 | % | VOUT ≈ 0.3V to VDD − 0.3V | 2 | |
| Internal Ladder Resistance | RLAD | 3.4 | 4.9 | 6.4 | kΩ | 2 | |
| Supply Voltage | VDD | 2.5 | 5.5 | V | 3 | ||
| Quiescent Current | IQ | 0.5 | 1 | 1.35 | mA | IO = 0 | 3 |
| Quiescent Current, Shutdown Mode | IQ_SHDN | 0.5 | 1 | µA | IO = 0 | 3 | |
| POR Trip Voltage | VPOR | 1.2 | 1.7 | 2.2 | V | 3 | |
| Supply Voltage VDD - VSS | VDD - VSS | 7 | V | 2 | |||
| Current at Input Pins | -2 | 2 | mA | 2 | |||
| Current at Output and Supply Pins | -30 | 30 | mA | 2 | |||
| Storage Temperature | -65 | 150 | °C | 2 | |||
| Junction Temperature | 150 | °C | 2 | ||||
| Input Offset Voltage Drift | ∆VOS/∆TA | 4 | µV/°C | TA = -40 to +85°C | 2 | ||
| DC Gain Drift G = +1 | ∆G/∆TA | 0.0002 | %/°C | TA = -40 to +85°C | 2 | ||
| DC Gain Drift G ≥ +2 | ∆G/∆TA | 0.0004 | %/°C | TA = -40 to +85°C | 2 | ||
| Internal Ladder Resistance Drift | ∆RLAD/∆TA | 0.028 | %/°C | TA = -40 to +85°C | 2 | ||
| Short-Circuit Current | IO(SC) | 30 | mA | 2 | |||
| POR Trip Voltage Drift | ∆VPOR/∆T | -3 | mV/°C | TA = -40°C to +85°C | 3 | ||
| Slew Rate G = 1 and 2 | SR | 4 | V/µs | G = 1 and 2 | 3 | ||
| Input Noise Voltage Density | eni | 10 | nV/√Hz | f = 10 kHz | 3 |
CAD (KiCad official)
- Symbol:
MCP6S21-I - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp6s21-i-etched.step/mcp6s21-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp6s21-i.step/mcp6s21-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (42 pp, sha256
09b51517a9b5e741, retrieved 2026-10-23, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP6S21-I
**Microchip Tech** · Operational Amplifier · SOIC-8
MCP6S21-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Analog output, a low-impedance voltage source whose value is set by the selected gain, the selected input and the VREF voltage. |
| 2 | CH0 | input | Analog input (the only channel on the MCP6S21), a high-impedance, low-bias-current CMOS input that can range from VSS-0.3V to VDD+0.3V. |
| 3 | VREF | power_in | External reference voltage pin, which should be between VSS and VDD and shifts the output voltage. |
| 4 | VSS | power_in | Negative supply, normally grounded in single-supply use. |
| 5 | CS | input | SPI chip select, a Schmitt-trigger CMOS logic input; taking it low starts communication and raising it executes the command. |
| 6 | SI | input | SPI serial data input, a Schmitt-trigger CMOS logic input clocked in on the rising edge of SCK. |
| 7 | SCK | input | SPI clock input, a Schmitt-trigger CMOS logic input with a maximum frequency of 10 MHz at VDD = 5V. |
| 8 | VDD | power_in | Positive supply, 2.5V to 5.5V above VSS, with a 0.1 µF bypass capacitor placed close to the pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Amplifiers |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | VOS | -275 | | 275 | µV | G = +1, VDD = 4.0V | 2 |
| Power Supply Rejection Ratio | PSRR | 70 | 85 | | dB | G = +1 | 2 |
| Input Bias Current over temperature | IB | | | 250 | pA | TA = -40 to +85°C, CHx = VDD/2 | 2 |
| DC Gain Error G = +1 | gE | -0.1 | | 0.1 | % | VOUT ≈ 0.3V to VDD − 0.3V | 2 |
| DC Gain Error G ≥ +2 | gE | -1 | | 1 | % | VOUT ≈ 0.3V to VDD − 0.3V | 2 |
| Internal Ladder Resistance | RLAD | 3.4 | 4.9 | 6.4 | kΩ | | 2 |
| Supply Voltage | VDD | 2.5 | | 5.5 | V | | 3 |
| Quiescent Current | IQ | 0.5 | 1 | 1.35 | mA | IO = 0 | 3 |
| Quiescent Current, Shutdown Mode | IQ_SHDN | | 0.5 | 1 | µA | IO = 0 | 3 |
| POR Trip Voltage | VPOR | 1.2 | 1.7 | 2.2 | V | | 3 |
| Supply Voltage VDD - VSS | VDD - VSS | | | 7 | V | | 2 |
| Current at Input Pins | | -2 | | 2 | mA | | 2 |
| Current at Output and Supply Pins | | -30 | | 30 | mA | | 2 |
| Storage Temperature | | -65 | | 150 | °C | | 2 |
| Junction Temperature | | | | 150 | °C | | 2 |
| Input Offset Voltage Drift | ∆VOS/∆TA | | 4 | | µV/°C | TA = -40 to +85°C | 2 |
| DC Gain Drift G = +1 | ∆G/∆TA | | 0.0002 | | %/°C | TA = -40 to +85°C | 2 |
| DC Gain Drift G ≥ +2 | ∆G/∆TA | | 0.0004 | | %/°C | TA = -40 to +85°C | 2 |
| Internal Ladder Resistance Drift | ∆RLAD/∆TA | | 0.028 | | %/°C | TA = -40 to +85°C | 2 |
| Short-Circuit Current | IO(SC) | | 30 | | mA | | 2 |
| POR Trip Voltage Drift | ∆VPOR/∆T | | -3 | | mV/°C | TA = -40°C to +85°C | 3 |
| Slew Rate G = 1 and 2 | SR | | 4 | | V/µs | G = 1 and 2 | 3 |
| Input Noise Voltage Density | eni | | 10 | | nV/√Hz | f = 10 kHz | 3 |
## CAD (KiCad official)
- Symbol: `MCP6S21-I`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `mcp6s21-i-etched.step` / `mcp6s21-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp6s21-i.step` / `mcp6s21-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mcp6s21-i-datasheet.pdf) (42 pp, sha256 `09b51517a9b5e741`, retrieved 2026-10-23, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp6s21-i-datasheet.pdf)